公开(公告)号：US06885605B2

公开(公告)日：2005-04-26

申请号：US10255999

申请日：2002-09-26

申请人： Kang Seol Lee ,  Jae Jin Lee ,  Kee Teok Park

发明人： Kang Seol Lee ,  Jae Jin Lee ,  Kee Teok Park

IPC分类号： H03K19/00 ,  G11C5/14 ,  G11C7/00 ,  G11C7/20 ,  G11C11/407 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4193

CPC分类号： G11C11/4074 ,  G11C7/20 ,  G11C11/4072 ,  G11C2207/2227

摘要： A power-up signal generator uses a deep power down power-up signal, which should be in a standby state in a deep power down entry, for an initialization of other semiconductor elements in a DRAM device that operates after an internal power supply voltage is generated. The generator also uses the power-up signal, which is disabled in the deep power down entry and enabled in a deep power down exit by the internal power supply voltage. The generator may include a power-up detector for generating a power-up detection signal, a deep power down power-up signal generator for generating a deep power down power-up signal, a power-up signal generator for generating a power-up signal and a power-up controller for determining whether or not to enable the power-up signal in the deep power down entry.

摘要翻译： 上电信号发生器使用深度掉电加电信号，其将处于深功率下降条目中的待机状态，用于在内部电源电压为内部操作的DRAM器件中的其它半导体元件的初始化 生成。 发电机还使用上电信号，该信号在深度掉电输入中被禁用，并通过内部电源电压在深度断电输出中使能。 该发生器可以包括用于产生上电检测信号的上电检测器，用于产生深度掉电上电信号的深度断电上电信号发生器，用于产生上电的上电信号发生器 信号和上电控制器，用于确定是否在深度断电输入中启用上电信号。

公开(公告)号：US07382677B2

公开(公告)日：2008-06-03

申请号：US11544284

申请日：2006-10-06

申请人： Kang Seol Lee ,  Kee Teok Park

发明人： Kang Seol Lee ,  Kee Teok Park

IPC分类号： G11C7/00

CPC分类号： G11C5/147 ,  G11C5/143

摘要： A internal voltage generator in a semiconductor memory device has a first and second internal voltage generators. The first internal voltage generator outputs a first signal having a first voltage level to internal circuits of the memory device during an active mode of the memory device operation. The second internal voltage generator outputs a second signal having a second voltage level to the internal circuits of the memory device; however, the second signal is interrupted in absence of a predetermined level of a power control signal during the active mode of the memory device operation. The internal voltage control unit monitors the operational signals generated by the memory device and outputs the predetermined level of the power control signal during a plurality of active sections of the active mode of the memory device operation requiring power.

摘要翻译： 半导体存储器件中的内部电压发生器具有第一和第二内部电压发生器。 第一内部电压发生器在存储器件操作的活动模式期间向存储器件的内部电路输出具有第一电压电平的第一信号。 第二内部电压发生器向存储器件的内部电路输出具有第二电压电平的第二信号; 然而，在存储器件操作的活动模式期间，在没有功率控制信号的预定电平的情况下，第二信号被中断。 内部电压控制单元监视存储器件产生的操作信号，并且在需要电力的存储器件操作的活动模式的多个有效部分期间输出功率控制信号的预定电平。

公开(公告)号：US06943585B2

公开(公告)日：2005-09-13

申请号：US10694966

申请日：2003-10-28

申请人： Jae Jin Lee ,  Kang Seol Lee

发明人： Jae Jin Lee ,  Kang Seol Lee

IPC分类号： H03K19/018 ,  G11C7/10 ,  H03K19/00 ,  H03K19/0948

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C2207/2227 ,  H03K19/0016

摘要： Disclosed is an input apparatus used in a SSTL interface, which comprises a differential buffer for comparing an external input signal with a reference potential inputted from an external, and a CMOS buffer for buffering the external input signal. In the input apparatus, the CMOS buffer operates when a command signal or an address signal is not inputted from an external, and when a predetermined operation such as a refresh operation is performed, thereby reducing the power consumption in a standby mode. Further, in order to prevent the input apparatus from abnormally operating when the reference potential is not maintained in the normal operation range, a reference potential level detecting circuit is further included in the input apparatus, so that the CMOS buffer operates when the reference potential deviates from a predetermined normal operation range. Furthermore, in order to enable an input buffer to operate as the CMOS when an input signal fully swings, a circuit for detecting a potential of an input signal inputted from an external is further included in the input apparatus.

摘要翻译： 公开了一种在SSTL接口中使用的输入装置，其包括用于将外部输入信号与从外部输入的参考电位进行比较的差分缓冲器和用于缓冲外部输入信号的CMOS缓冲器。 在输入装置中，当没有从外部输入命令信号或地址信号时，并且当执行诸如刷新操作的预定操作时，CMOS缓冲器操作，从而降低待机模式下的功耗。 此外，为了防止输入装置在基准电位不保持在正常工作范围时异常工作，在输入装置中还包括基准电位电平检测电路，使得CMOS缓冲器在参考电位偏移 从预定的正常操作范围。 此外，为了使输入缓冲器在输入信号完全摆动时作为CMOS工作，在输入装置中还包括用于检测从外部输入的输入信号的电位的电路。

公开(公告)号：US06721211B2

公开(公告)日：2004-04-13

申请号：US10246083

申请日：2002-09-18

申请人： Jae Jin Lee ,  Kang Seol Lee

发明人： Jae Jin Lee ,  Kang Seol Lee

IPC分类号： G11C700

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C11/4074 ,  G11C11/4096 ,  H02M3/07 ,  H02M2003/072

摘要： A voltage generator for a semiconductor memory device that improves the drivability of an output driver by controlling a gate of the output driver to vary between an internal power supply voltage and a ground voltage, is disclosed. The voltage generator includes an output voltage controller to generate a pull-up signal for controlling a pull-up operation and a pull-down signal for controlling a pull-down operation, the pull-up signal having a level substantially equivalent to an internal power supply voltage if a cell plate voltage is higher than a cell plate reference voltage, and having a level below the cell plate voltage if the cell plate voltage is lower than the cell plate reference voltage. The voltage generator further includes an output driver to generate a stable cell plate voltage in response to the pull-up signal and the pull-down signal.

摘要翻译： 公开了一种用于半导体存储器件的电压发生器，其通过控制输出驱动器的栅极在内部电源电压和接地电压之间变化来提高输出驱动器的驱动能力。 电压发生器包括输出电压控制器以产生用于控制上拉操作的上拉信号和用于控制下拉操作的下拉信号，所述上拉信号的电平基本上等于内部功率 如果单元板电压高于单元板参考电压，并且如果单元板电压低于单元板参考电压，则具有低于单元板电压的电平的电源电压。 电压发生器还包括输出驱动器，以响应于上拉信号和下拉信号产生稳定的单元板电压。

公开(公告)号：US08553478B2

公开(公告)日：2013-10-08

申请号：US13190169

申请日：2011-07-25

申请人： Tae Sik Yun ,  Kang Seol Lee

发明人： Tae Sik Yun ,  Kang Seol Lee

IPC分类号： G11C7/00

CPC分类号： G11C29/883 ,  G11C5/04 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit includes a first chip and a second chip stacked together with the first chip. A first memory area is formed on the second chip, and a second memory area for repairing a failure of the first memory area is formed on the first chip.

摘要翻译： 半导体集成电路包括与第一芯片堆叠在一起的第一芯片和第二芯片。 在第二芯片上形成第一存储区域，并且在第一芯片上形成用于修复第一存储区域的故障的第二存储区域。

公开(公告)号：US07969800B2

公开(公告)日：2011-06-28

申请号：US12493734

申请日：2009-06-29

申请人： Tae Sik Yun ,  Kang Seol Lee

发明人： Tae Sik Yun ,  Kang Seol Lee

IPC分类号： G11C7/00

CPC分类号： G11C8/18

摘要： A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a cell block and a second input/output line extending to the outside of the cell block. The cell array also including a bit line switch for connecting a bit line pair to each other. The input/output line switch and the bit line switch are further controlled by the line connection control signal from the row path activating unit.

摘要翻译： 一种半导体存储装置，包括：行路径激活部，被配置为根据接收到的地址和主动命令生成线路连接控制信号。 半导体存储装置还包括一个单元阵列电路单元，包括用于连接单元块中的第一输入/输出线和延伸到单元块外部的第二输入/输出线的输入/输出线开关。 单元阵列还包括用于将位线对彼此连接的位线开关。 输入/输出线路开关和位线开关进一步由来自行路径激活单元的线路连接控制信号控制。

公开(公告)号：US07898287B2

公开(公告)日：2011-03-01

申请号：US12291731

申请日：2008-11-13

申请人： Ki Ho Kim ,  Kang Seol Lee

发明人： Ki Ho Kim ,  Kang Seol Lee

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/00323 ,  H03K19/018564

摘要： An input buffer includes a delay compensation unit for combining (a) a first signal obtained by buffering an input signal using another signal, which is out of phase with the input signal, with (b) a second signal obtained by buffering the input signal using a reference voltage signal, to output a third signal.

摘要翻译： 输入缓冲器包括延迟补偿单元，用于组合（a）通过使用与输入信号异相的另一信号来缓冲输入信号而获得的第一信号，（b）通过使用 参考电压信号，以输出第三信号。

公开(公告)号：US07545199B2

公开(公告)日：2009-06-09

申请号：US10980408

申请日：2004-11-03

申请人： Kang Seol Lee ,  Yong Mi Kim

发明人： Kang Seol Lee ,  Yong Mi Kim

IPC分类号： G11C5/14

CPC分类号： G11C11/4074 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/075

摘要： Disclosed are a power supply circuit for an oscillator of a semiconductor memory device and a voltage pumping device using the same. In the power supply circuit, a voltage divider divides a voltage between an external power supply and ground. A driver is controlled by a signal of the voltage divided by the voltage divider. The driver supplies an internal power supply voltage. A capacitor is coupled between the driver and the ground. As the level of an external power supply voltage is increased, a relatively low voltage is supplied to the oscillator to increase a cycle length of an output pulse signal of the oscillator. Therefore, an excessive increase in the internal power supply voltage due to over-pumping can be avoided and noise occurrence and electric current consumption can be reduced.

摘要翻译： 公开了一种用于半导体存储器件的振荡器的电源电路和使用该电源的电压泵送装置。 在电源电路中，分压器分隔外部电源和地之间的电压。 驱动器由分压器分压的信号控制。 驱动器提供内部电源电压。 电容器连接在驱动器和地之间。 随着外部电源电压的电平升高，向振荡器提供相对低的电压以增加振荡器的输出脉冲信号的周期长度。 因此，可以避免由于过度泵浦引起的内部电源电压的过度增加，并且可以降低噪声发生和电流消耗。

公开(公告)号：US08964449B2

公开(公告)日：2015-02-24

申请号：US13355781

申请日：2012-01-23

申请人： Tae Sik Yun ,  Kang Seol Lee

发明人： Tae Sik Yun ,  Kang Seol Lee

IPC分类号： G11C11/24 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4099

CPC分类号： G11C11/4076 ,  G11C11/4091 ,  G11C11/4099

摘要： A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The semiconductor memory device comprises a selected memory cell connected to a first bit line and a first word line, a dummy memory cell connected to a second bit line complementary to the first bit line and a second word line, and a sense amplifier connected to the first and second bit lines and configured to read data stored in the selected memory cell by simultaneously enablement of the first and second word lines.

摘要翻译： 半导体存储器件选择多个存储单元中的一个作为虚拟存储单元。 虚拟存储器单元连接到与连接到所选存储单元的位线互补的位线。 该技术有利地补偿位线的电容。 半导体存储器件包括连接到第一位线和第一字线的选定存储器单元，连接到与第一位线互补的第二位线和第二字线的虚拟存储器单元，以及连接到第一位线的读出放大器 第一和第二位线，并且被配置为通过同时启用第一和第二字线来读取存储在所选存储单元中的数据。

公开(公告)号：US08724409B2

公开(公告)日：2014-05-13

申请号：US12947441

申请日：2010-11-16

申请人： Kang Seol Lee ,  Jae Hyuk Im

发明人： Kang Seol Lee ,  Jae Hyuk Im

IPC分类号： G11C7/00 ,  G11C29/00 ,  G05F3/16 ,  G05F3/20

CPC分类号： H03K19/00384

摘要： A semiconductor integrated circuit includes an internal reference voltage generation unit configured to generate an internal reference voltage; a high voltage generation unit configured to pump an external driving voltage based on the internal reference voltage applied from the internal reference voltage generation unit, and generate a high voltage having a specified level; and a reference voltage transfer unit configured to generate a test reference voltage from a reference voltage in a package test mode to correspond to a change in a driving operation of the external driving voltage applied from outside, and monitor and force the internal reference voltage.

摘要翻译： 半导体集成电路包括：内部参考电压生成单元，被配置为产生内部参考电压; 高电压产生单元，被配置为基于从内部参考电压产生单元施加的内部参考电压来泵浦外部驱动电压，并产生具有指定电平的高电压; 以及参考电压传送单元，被配置为在封装测试模式下从参考电压产生测试参考电压，以对应于从外部施加的外部驱动电压的驱动操作的变化，并监视和强制内部参考电压。