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1.发明授权Semiconductor device with epitaxial source/drain facetting provided at the gate edge 有权具有外延源/漏极平面的半导体器件设置在栅极边缘公开(公告)号：US08916443B2
公开(公告)日：2014-12-23
申请号：US13534407
申请日：2012-06-27
IPC分类号： H01L21/8238 , H01L27/12 , G06F17/50
CPC分类号： H01L29/0847 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L23/485 , H01L27/1203 , H01L29/0653
摘要： A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate structures and at least one trench that extends through the raised region and through the active region is formed, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor. The first raised region and second raised region are electrically isolated by the at least one trench.
摘要翻译： 形成半导体结构的方法包括提供有源层并在有源层上形成相邻的栅极结构。 栅极结构各自具有侧壁，使得第一间隔件形成在侧壁上。 凸起区域在相邻栅极结构之间的有源层上外延生长，并且形成延伸穿过凸起区域并通过有源区域的至少一个沟槽，由此至少一个沟槽将凸起区域分隔成对应于第一凸起区域 涉及对应于第二晶体管的第一晶体管和第二升高区域。 第一凸起区域和第二凸起区域由至少一个沟槽电隔离。
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公开(公告)号：US08962434B2
公开(公告)日：2015-02-24
申请号：US13545224
申请日：2012-07-10
IPC分类号： H01L21/336
CPC分类号： H01L27/088 , H01L21/02529 , H01L21/02532 , H01L21/0257 , H01L21/02576 , H01L21/02579 , H01L21/28008 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L21/84 , H01L29/167 , H01L29/6653 , H01L29/66545 , H01L29/66606 , H01L29/7834 , H01L29/7848
摘要： A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.
摘要翻译： 一种包括提供包括第一半导体器件和第二半导体器件的半导体衬底的方法，所述第一和第二半导体器件包括虚设衬垫，虚拟栅极和延伸区域; 用掩模保护第二半导体器件; 从第一半导体器件去除虚设间隔物; 以及在所述第一半导体器件的所述延伸区域的顶部上沉积原位掺杂的外延区域。
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公开(公告)号：US20140015014A1
公开(公告)日：2014-01-16
申请号：US13545224
申请日：2012-07-10
IPC分类号： H01L21/20 , H01L21/336 , H01L29/78
CPC分类号： H01L27/088 , H01L21/02529 , H01L21/02532 , H01L21/0257 , H01L21/02576 , H01L21/02579 , H01L21/28008 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L21/84 , H01L29/167 , H01L29/6653 , H01L29/66545 , H01L29/66606 , H01L29/7834 , H01L29/7848
摘要： A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.
摘要翻译： 一种包括提供包括第一半导体器件和第二半导体器件的半导体衬底的方法，所述第一和第二半导体器件包括虚设衬垫，虚拟栅极和延伸区域; 用掩模保护第二半导体器件; 从第一半导体器件去除虚设间隔物; 以及在所述第一半导体器件的所述延伸区域的顶部上沉积原位掺杂的外延区域。
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4.发明申请SEMICONDUCTOR DEVICE WITH EPITAXIAL SOURCE/DRAIN FACETTING PROVIDED AT THE GATE EDGE 有权封闭边缘提供外延源/排水沟的半导体器件公开(公告)号：US20140001554A1
公开(公告)日：2014-01-02
申请号：US13534407
申请日：2012-06-27
IPC分类号： H01L21/8238 , G06F17/50 , H01L27/12
CPC分类号： H01L29/0847 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L23/485 , H01L27/1203 , H01L29/0653
摘要： A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate structures and at least one trench that extends through the raised region and through the active region is formed, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor. The first raised region and second raised region are electrically isolated by the at least one trench.
摘要翻译： 形成半导体结构的方法包括提供有源层并在有源层上形成相邻的栅极结构。 栅极结构各自具有侧壁，使得第一间隔件形成在侧壁上。 凸起区域在相邻栅极结构之间的有源层上外延生长，并且形成延伸穿过凸起区域并通过有源区域的至少一个沟槽，由此至少一个沟槽将凸起区域分隔成对应于第一凸起区域 涉及对应于第二晶体管的第一晶体管和第二升高区域。 第一凸起区域和第二凸起区域由至少一个沟槽电隔离。
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5.发明授权Thin semiconductor-on-insulator MOSFET with co-integrated silicon, silicon germanium and silicon doped with carbon channels 有权具有共同集成硅，硅锗和掺杂碳通道的硅的薄绝缘体MOSFET公开(公告)号：US08866227B2
公开(公告)日：2014-10-21
申请号：US13607743
申请日：2012-09-09
申请人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/84 , H01L21/77 , H01L27/092 , H01L21/02 , H01L21/8234
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/77 , H01L21/823412 , H01L27/092
摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.
摘要翻译： 一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域 以及掺杂有碳层的硅的第三器件区域。 然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。 可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。 可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。
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6.发明申请THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS 有权具有合并硅，半导体和绝缘体的半导体绝缘体MOSFET，具有碳通道公开(公告)号：US20130099319A1
公开(公告)日：2013-04-25
申请号：US13607743
申请日：2012-09-09
申请人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/77 , H01L21/823412 , H01L27/092
摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.
摘要翻译： 一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域 以及掺杂有碳层的硅的第三器件区域。 然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。 可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。 可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。
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7.发明申请公开(公告)号：US20130099318A1
公开(公告)日：2013-04-25
申请号：US13280850
申请日：2011-10-25
申请人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L27/092 , H01L21/20
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/77 , H01L21/823412 , H01L27/092
摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.
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公开(公告)号：US08445971B2
公开(公告)日：2013-05-21
申请号：US13237319
申请日：2011-09-20
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/41783 , H01L29/165 , H01L29/41775 , H01L29/66628 , H01L29/66772 , H01L29/78654
摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.
摘要翻译： 一种用于制造场效应晶体管器件的方法，包括在衬底上形成栅极叠层，在衬底上邻近栅堆叠形成间隔物，在衬底上形成有源区的第一部分，有源区的第一部分 具有邻近所述栅叠层的第一刻面，在所述有源区的所述第一部分的一部分上形成所述有源区的第二部分，所述有源区的所述第二部分具有邻近所述栅叠层的第二刻面， 第一小面表面和第二小面表面部分地限定与栅极叠层相邻的空腔。
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公开(公告)号：US20130071979A1
公开(公告)日：2013-03-21
申请号：US13606382
申请日：2012-09-07
IPC分类号： H01L21/336
CPC分类号： H01L29/41783 , H01L29/165 , H01L29/41775 , H01L29/66628 , H01L29/66772 , H01L29/78654
摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.
摘要翻译： 一种用于制造场效应晶体管器件的方法，包括在衬底上形成栅极叠层，在衬底上邻近栅堆叠形成间隔物，在衬底上形成有源区的第一部分，有源区的第一部分 具有邻近所述栅叠层的第一刻面，在所述有源区的所述第一部分的一部分上形成所述有源区的第二部分，所述有源区的所述第二部分具有邻近所述栅叠层的第二刻面， 第一小面表面和第二小面表面部分地限定与栅极叠层相邻的空腔。
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公开(公告)号：US08563385B2
公开(公告)日：2013-10-22
申请号：US13606382
申请日：2012-09-07
IPC分类号： H01L21/336
CPC分类号： H01L29/41783 , H01L29/165 , H01L29/41775 , H01L29/66628 , H01L29/66772 , H01L29/78654
摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.
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