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    Semiconductor structure having NFET and PFET formed in SOI substrate with underlapped extensions
    1.
    发明授权
    Semiconductor structure having NFET and PFET formed in SOI substrate with underlapped extensions 失效
    具有NFET和PFET的半导体结构形成在具有延伸延伸的SOI衬底中

    公开(公告)号：US08598663B2

    公开(公告)日：2013-12-03

    申请号：US13108290

    申请日：2011-05-16

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L21/70

    CPC分类号： H01L27/1203 ,  H01L21/823864 ,  H01L21/823892

    摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.

    摘要翻译： 一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。 半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。 每个NFET和PFET下面也可以有一个阱。 存在将非零电偏压施加到SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

    SEMICONDUCTOR STRUCTURE HAVING UNDERLAPPED DEVICES
    2.
    发明申请
    SEMICONDUCTOR STRUCTURE HAVING UNDERLAPPED DEVICES 失效
    具有底层设备的半导体结构

    公开(公告)号：US20120292705A1

    公开(公告)日：2012-11-22

    申请号：US13108290

    申请日：2011-05-16

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L27/092

    CPC分类号： H01L27/1203 ,  H01L21/823864 ,  H01L21/823892

    摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the. SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.

    摘要翻译： 一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。 半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。 每个NFET和PFET下面也可以有一个阱。 有一个非零的电偏压被施加到。 SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

    SOI trench DRAM structure with backside strap
    3.
    发明授权
    SOI trench DRAM structure with backside strap 有权
    具有背面带的SOI沟槽DRAM结构

    公开(公告)号：US08318574B2

    公开(公告)日：2012-11-27

    申请号：US12847208

    申请日：2010-07-30

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L21/20

    CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/10867

    摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having of a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion of the top silicon layer, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.

    摘要翻译： 在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，背面带在背面的第一端耦合到顶部硅层的掺杂部分 带子和背部带子的第二端处的电容器; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。

    Same-Chip Multicharacteristic Semiconductor Structures
    5.
    发明申请
    Same-Chip Multicharacteristic Semiconductor Structures 有权
    同芯多特征半导体结构

    公开(公告)号：US20120049284A1

    公开(公告)日：2012-03-01

    申请号：US12861976

    申请日：2010-08-24

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L27/12 ,  H01L21/336

    CPC分类号： H01L27/1211 ,  H01L27/1203

    摘要： In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.

    摘要翻译： 在一个示例性实施例中，半导体结构包括：绝缘体上半导体衬底，具有覆盖绝缘层的顶部半导体层，绝缘层覆盖在底部衬底层上; 至少一个第一装置至少部分地覆盖并设置在顶部半导体层的第一部分上，其中第一部分具有第一厚度，第一宽度和第一深度; 以及至少一个第二装置，其至少部分地覆盖并设置在顶部半导体层的第二部分上，其中第二部分具有第二厚度，第二宽度和第二深度，其中以下至少一个成立：第一 厚度大于第二厚度，第一宽度大于第二宽度，第一深度大于第二深度。

    Strained thin body CMOS device having vertically raised source/drain stressors with single spacer
    8.
    发明授权
    Strained thin body CMOS device having vertically raised source/drain stressors with single spacer 有权
    应变的薄体CMOS器件具有单个间隔物的垂直升高的源/漏应力源

    公开(公告)号：US08546228B2

    公开(公告)日：2013-10-01

    申请号：US12816399

    申请日：2010-06-16

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66477 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618

    摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

    摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一 在图案化的栅极结构下方的半导体衬底的沟道区上。

    Thin channel device and fabrication method with a reverse embedded stressor
    10.
    发明授权
    Thin channel device and fabrication method with a reverse embedded stressor 有权
    具有反向嵌入式应力源的薄通道器件和制造方法

    公开(公告)号：US08383474B2

    公开(公告)日：2013-02-26

    申请号：US12789699

    申请日：2010-05-28

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7849 ,  H01L21/26506 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78654

    摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer. A removable buried layer is provided on or in the second semiconductor layer. A gate structure with side spacers is formed on the first semiconductor layer. Recesses are formed down to the removable buried layer in areas for source and drain regions. The removable buried layer is etched away to form an undercut below the dielectric layer below the gate structure. A stressor layer is formed in the undercut, and source and drain regions are formed.

    摘要翻译： 用于在半导体层中诱发应力的装置和方法包括提供在第一半导体层和第二半导体层之间形成介电层的基板。 可移除的掩埋层设置在第二半导体层上或第二半导体层中。 在第一半导体层上形成具有侧面间隔物的栅极结构。 在源区和漏区的区域中形成凹陷到可移除的掩埋层。 蚀刻掉可移除的掩埋层，以在栅极结构下面的介电层下方形成底切。 在底切中形成应力层，形成源区和漏区。