公开(公告)号：US20120292705A1

公开(公告)日：2012-11-22

申请号：US13108290

申请日：2011-05-16

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/092

CPC分类号： H01L27/1203 ,  H01L21/823864 ,  H01L21/823892

摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the. SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.

摘要翻译： 一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。 半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。 每个NFET和PFET下面也可以有一个阱。 有一个非零的电偏压被施加到。 SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

公开(公告)号：US08598663B2

公开(公告)日：2013-12-03

申请号：US13108290

申请日：2011-05-16

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L21/70

CPC分类号： H01L27/1203 ,  H01L21/823864 ,  H01L21/823892

摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.

摘要翻译： 一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。 半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。 每个NFET和PFET下面也可以有一个阱。 存在将非零电偏压施加到SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

公开(公告)号：US20110309333A1

公开(公告)日：2011-12-22

申请号：US12819440

申请日：2010-06-21

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC分类号： H01L29/775 ,  H01L21/34 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/78696

摘要： A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.

摘要翻译： 提供一种形成半导体器件的方法，其中用于源极和漏极区的掺杂剂从掺杂的介电层引入。 在一个示例中，栅极结构形成在半导体层的厚度小于10nm的SOI衬底的半导体层上。 在与栅极结构相邻的半导体层的至少一部分上形成掺杂介电层。 来自掺杂介电层的掺杂剂被驱动到与栅极结构相邻的半导体层的部分中。 扩散到半导体中的掺杂剂提供了源极和漏极延伸区域。

公开(公告)号：US08394710B2

公开(公告)日：2013-03-12

申请号：US12819440

申请日：2010-06-21

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/78696

摘要： A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.

摘要翻译： 提供一种形成半导体器件的方法，其中用于源极和漏极区的掺杂剂从掺杂的介电层引入。 在一个示例中，栅极结构形成在半导体层的厚度小于10nm的SOI衬底的半导体层上。 在与栅极结构相邻的半导体层的至少一部分上形成掺杂介电层。 来自掺杂介电层的掺杂剂被驱动到与栅极结构相邻的半导体层的部分中。 扩散到半导体中的掺杂剂提供了源极和漏极延伸区域。

公开(公告)号：US20130344677A1

公开(公告)日：2013-12-26

申请号：US13531780

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L21/762

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

公开(公告)号：US20130341754A1

公开(公告)日：2013-12-26

申请号：US13531654

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L29/06

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

公开(公告)号：US08455932B2

公开(公告)日：2013-06-04

申请号：US13102073

申请日：2011-05-06

申请人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Wilfried E. Haensch ,  Balasubramanian S. Haran ,  Pranita Kulkarni

发明人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Wilfried E. Haensch ,  Balasubramanian S. Haran ,  Pranita Kulkarni

IPC分类号： H01L21/336

CPC分类号： H01L27/0207 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/1104 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7834

摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.

摘要翻译： 采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。 局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。 此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。 局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。

公开(公告)号：US20130082311A1

公开(公告)日：2013-04-04

申请号：US13609747

申请日：2012-09-11

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7834

摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.

公开(公告)号：US08673738B2

公开(公告)日：2014-03-18

申请号：US13531780

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L21/76

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

摘要翻译： 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

公开(公告)号：US20130249002A1

公开(公告)日：2013-09-26

申请号：US13424447

申请日：2012-03-20

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0653 ,  H01L21/76224 ,  H01L21/84 ,  H01L29/66545

摘要： A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.

摘要翻译： 改进ETSOI MOSFET器件的结构和方法。 提供晶片，其包括具有覆盖在第二半导体层上的氧化物层的至少第一半导体层的区域。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔不完全落地，至少部分地延伸到STI中，并且绝缘材料沉积在所述孔中。