公开(公告)号：US07732872B2

公开(公告)日：2010-06-08

申请号：US11924053

申请日：2007-10-25

申请人： Kangguo Cheng ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

发明人： Kangguo Cheng ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L27/088

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.

摘要翻译： 在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。 在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整 氧化层。 还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。 在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

公开(公告)号：US20090108356A1

公开(公告)日：2009-04-30

申请号：US11924053

申请日：2007-10-25

申请人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

发明人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/44

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.

摘要翻译： 在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。 在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整 氧化层。 还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。 在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

公开(公告)号：US20090001466A1

公开(公告)日：2009-01-01

申请号：US11769914

申请日：2007-06-28

申请人： Haining S. Yang ,  Ramachandra Divakaruni ,  Byeong Y. Kim ,  Junedong Lee ,  Gaku Sudo

发明人： Haining S. Yang ,  Ramachandra Divakaruni ,  Byeong Y. Kim ,  Junedong Lee ,  Gaku Sudo

IPC分类号： H01L21/4763 ,  H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/84 ,  H01L29/7843

摘要： A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region shares an edge with the SOI layer. A dielectric layer then is deposited atop the conformal layer and the trench isolation region, after which a second opening is formed which is aligned with the first opening, the second opening extending through the dielectric layer to expose the bulk semiconductor region. Finally, the conductive via is formed in the second opening.

摘要翻译： 提供了形成用于接触绝缘体上半导体（“SOI”）衬底的体半导体区域的导电通孔的方法。 第一开口形成在覆盖沟槽隔离区域的共形层中，其中沟槽隔离区域与SOI层共享边缘。 然后在保形层和沟槽隔离区的顶部沉积电介质层，然后形成与第一开口对准的第二开口，第二开口延伸穿过电介质层以暴露体半导体区域。 最后，在第二开口中形成导电通孔。

公开(公告)号：US20090206442A1

公开(公告)日：2009-08-20

申请号：US12033322

申请日：2008-02-19

申请人： Ramachandra Divakaruni ,  Wai-Kin Li ,  Haining S. Yang

发明人： Ramachandra Divakaruni ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01L21/762 ,  H01L23/58

CPC分类号： H01L21/76232

摘要： A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate.

摘要翻译： 一种形成用于半导体器件的浅沟槽隔离（STI）区域的方法，所述方法包括在半导体衬底内限定STI沟槽开口; 用初始沟槽填充材料填充STI沟槽开口; 在对应于STI沟槽开口的位置处限定衬底上的纳米尺度开口的图案; 将纳米级开口的图案转移到沟槽填充材料中，以便在沟槽填充材料中限定多个垂直取向的纳米级开口; 并用另外的沟槽填充材料堵塞纳米级开口的上部，从而在衬底中限定多孔STI区域。

公开(公告)号：US07871895B2

公开(公告)日：2011-01-18

申请号：US12033322

申请日：2008-02-19

申请人： Ramachandra Divakaruni ,  Wai-Kin Li ,  Haining S. Yang

发明人： Ramachandra Divakaruni ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76232

摘要： A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate.

摘要翻译： 一种形成用于半导体器件的浅沟槽隔离（STI）区域的方法，所述方法包括在半导体衬底内限定STI沟槽开口; 用初始沟槽填充材料填充STI沟槽开口; 在对应于STI沟槽开口的位置处限定衬底上的纳米尺度开口的图案; 将纳米级开口的图案转移到沟槽填充材料中，以便在沟槽填充材料中限定多个垂直取向的纳米级开口; 并用另外的沟槽填充材料堵塞纳米级开口的上部，从而在衬底中限定多孔STI区域。

公开(公告)号：US07867893B2

公开(公告)日：2011-01-11

申请号：US11769914

申请日：2007-06-28

申请人： Haining S. Yang ,  Ramachandra Divakaruni ,  Byeong Y. Kim ,  Junedong Lee ,  Gaku Sudo

发明人： Haining S. Yang ,  Ramachandra Divakaruni ,  Byeong Y. Kim ,  Junedong Lee ,  Gaku Sudo

IPC分类号： H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/84 ,  H01L29/7843

摘要： A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region shares an edge with the SOI layer. A dielectric layer then is deposited atop the conformal layer and the trench isolation region, after which a second opening is formed which is aligned with the first opening, the second opening extending through the dielectric layer to expose the bulk semiconductor region. Finally, the conductive via is formed in the second opening.

摘要翻译： 提供了形成用于接触绝缘体上半导体（“SOI”）衬底的体半导体区域的导电通孔的方法。 第一开口形成在覆盖沟槽隔离区域的共形层中，其中沟槽隔离区域与SOI层共享边缘。 然后在保形层和沟槽隔离区的顶部沉积电介质层，然后形成与第一开口对准的第二开口，第二开口延伸穿过电介质层以暴露体半导体区域。 最后，在第二开口中形成导电通孔。

公开(公告)号：US08674444B2

公开(公告)日：2014-03-18

申请号：US13422297

申请日：2012-03-16

申请人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

发明人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

IPC分类号： H01L27/12

CPC分类号： H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

摘要： A semiconductor structure includes a semiconductor substrate. A conductive gate abuts a gate insulator for controlling conduction of a channel region. The gate insulator abuts the channel region. A source region and a drain region are associated with the conductive gate. The source region includes a first material and the drain region includes a second material. The conductive gate is self-aligned to the first and the second material.

摘要翻译： 半导体结构包括半导体衬底。 导电栅极邻接栅极绝缘体，用于控制沟道区的导通。 栅极绝缘体邻接沟道区域。 源极区域和漏极区域与导电栅极相关联。 源极区域包括第一材料，漏极区域包括第二材料。 导电栅极与第一和第二材料自对准。

公开(公告)号：US08461625B2

公开(公告)日：2013-06-11

申请号：US13080352

申请日：2011-04-05

申请人： Kangguo Cheng ,  Haining S. Yang

发明人： Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L29/78

CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L29/7845 ,  Y10S438/926

摘要： An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.

摘要翻译： 提供了具有应力增强通道的集成电路，设计结构和制造集成电路的方法。 该方法包括在衬底上形成虚拟栅极结构并在虚拟栅极结构中形成沟槽。 该方法还包括用应变诱导材料填充沟槽的一部分并用栅极材料填充沟槽的剩余部分。

公开(公告)号：US20120235236A1

公开(公告)日：2012-09-20

申请号：US13422297

申请日：2012-03-16

申请人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

发明人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

摘要： A semiconductor structure includes a semiconductor substrate. A conductive gate abuts a gate insulator for controlling conduction of a channel region. The gate insulator abuts the channel region. A source region and a drain region are associated with the conductive gate. The source region includes a first material and the drain region includes a second material. The conductive gate is self-aligned to the first and the second material.

摘要翻译： 半导体结构包括半导体衬底。 导电栅极邻接栅极绝缘体，用于控制沟道区的导通。 栅极绝缘体邻接沟道区域。 源极区域和漏极区域与导电栅极相关联。 源极区域包括第一材料，漏极区域包括第二材料。 导电栅极与第一和第二材料自对准。

公开(公告)号：US08232210B2

公开(公告)日：2012-07-31

申请号：US12562222

申请日：2009-09-18

申请人： Kangguo Cheng ,  Haining S. Yang

发明人： Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/265 ,  H01L21/28008 ,  H01L21/32139 ,  H01L21/76816

摘要： A method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features.

摘要翻译： 形成集成电路（IC）器件特征的方法包括：在待图案化的半导体器件层上形成初始基本平坦的硬掩模层; 在所述硬掩模层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层中的第一组半导体器件特征; 在硬掩模层中以保持硬掩模层基本上平面的方式对准第一组半导体器件特征; 去除第一光致抗蚀剂层; 在所述基本上平坦的硬掩模层上形成第二光致抗蚀剂层; 在第二光致抗蚀剂层中图形化第二组半导体器件特征; 在硬掩模层中以保持硬掩模层基本上平面的方式对准第二组半导体器件特征; 去除所述第二光致抗蚀剂层; 以及通过移除与所述第一和第二组半导体器件特征对应的部分来在所述硬掩模层内产生形貌。