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公开(公告)号：US07285817B2
公开(公告)日：2007-10-23
申请号：US11223679
申请日：2005-09-09
IPC分类号： H01L29/788
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric and having a predetermined pattern. The second shading layer has such a pattern that the second shading layer is positioned at least between the adjacent first shading layers.
摘要翻译： 半导体器件包括：具有阴影目标区域的半导体层; 设置在阴影对象区域的半导体层上的半导体元件; 设置在所述半导体元件上的第一层间电介质; 设置在所述第一层间电介质上的多个第一遮光层; 至少设置在第一遮光层上的第二层间电介质; 以及设置在第二层间电介质上并具有预定图案的第二遮光层。 第二遮光层具有使第二遮光层至少位于相邻的第一遮光层之间的图案。
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公开(公告)号：US20080012141A1
公开(公告)日：2008-01-17
申请号：US11901477
申请日：2007-09-17
IPC分类号： H01L23/52
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric and having a predetermined pattern. The second shading layer has such a pattern that the second shading layer is positioned at least between the adjacent first shading layers.
摘要翻译： 半导体器件包括：具有阴影目标区域的半导体层; 设置在阴影对象区域的半导体层上的半导体元件; 设置在所述半导体元件上的第一层间电介质; 设置在所述第一层间电介质上的多个第一遮光层; 至少设置在第一遮光层上的第二层间电介质; 以及设置在第二层间电介质上并具有预定图案的第二遮光层。 第二遮光层具有使第二遮光层至少位于相邻的第一遮光层之间的图案。
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公开(公告)号：US20060055044A1
公开(公告)日：2006-03-16
申请号：US11223679
申请日：2005-09-09
IPC分类号： H01L23/52
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric and having a predetermined pattern. The second shading layer has such a pattern that the second shading layer is positioned at least between the adjacent first shading layers.
摘要翻译： 半导体器件包括：具有阴影目标区域的半导体层; 设置在阴影对象区域的半导体层上的半导体元件; 设置在所述半导体元件上的第一层间电介质; 设置在所述第一层间电介质上的多个第一遮光层; 至少设置在第一遮光层上的第二层间电介质; 以及设置在第二层间电介质上并具有预定图案的第二遮光层。 第二遮光层具有使第二遮光层至少位于相邻的第一遮光层之间的图案。
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公开(公告)号：US07531864B2
公开(公告)日：2009-05-12
申请号：US11148302
申请日：2005-06-09
IPC分类号： H01L29/76
CPC分类号： H01L21/28273 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/7883
摘要： A nonvolatile memory device includes: a semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer; a semiconductor section of a second conductivity type provided in the first region and functioning as a control gate; a semiconductor section of the first conductivity type provided in the second region; a semiconductor section of the second conductivity type provided in the third region; an insulating layer provided on the semiconductor layer in the first to third regions; a floating gate electrode provided on the insulating layer across the first to third regions; impurity regions of the first conductivity type provided on each side of the floating gate electrode in the first region; impurity regions of the second conductivity type provided on each side of the floating gate electrode in the second region and functioning as either a source region or a drain region; and impurity regions of the first conductivity type provided on each side of the floating gate electrode in the third region and functioning as either a source region or a drain region.
摘要翻译： 非易失性存储器件包括：第一导电类型的半导体层，其中第一区域，第二区域和第三区域被隔离绝缘层分隔; 第二导电类型的半导体部分，设置在第一区域中并用作控制栅极; 设置在第二区域中的第一导电类型的半导体部分; 设置在第三区域中的第二导电类型的半导体部分; 设置在第一至第三区域的半导体层上的绝缘层; 在第一至第三区域上设置在绝缘层上的浮栅电极; 设置在第一区域中的浮置栅电极的每一侧上的第一导电类型的杂质区域; 第二导电类型的杂质区域设置在第二区域中的浮置栅电极的每一侧上并且用作源极区域或漏极区域; 以及设置在第三区域中的浮栅的每一侧上的第一导电类型的杂质区，并且用作源区或漏区。
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5.发明授权Nonvolatile memory device and data write method for nonvolatile memory device 有权非易失性存储器件和非易失性存储器件的数据写入方法公开(公告)号：US07292475B2
公开(公告)日：2007-11-06
申请号：US11176324
申请日：2005-07-08
CPC分类号： G11C16/0433
摘要： A nonvolatile memory device, including a plurality of memory cell blocks, N memory cell blocks (N is an integer equal to or greater than 2) being arranged in a row direction, L memory cell blocks (L is an integer equal to or greater than 2) being arranged in a column direction, and each of the memory cell blocks including M memory cells (M is an integer equal to or greater than 2), a plurality of wordlines, a plurality of first control gate lines, a plurality of first control gate switches, a plurality of second control gate lines, and a plurality of bitlines.
摘要翻译： 包括多个存储单元块的非易失性存储器件，N个存储单元块（N是等于或大于2的整数）被排列成行方向，L个存储单元块（L是等于或大于 2）沿列方向布置，并且每个存储单元块包括M个存储单元（M是等于或大于2的整数），多个字线，多个第一控制栅极线，多个第一 控制栅极开关，多个第二控制栅极线和多个位线。
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6.发明申请Nonvolatile memory device and data write method for nonvolatile memory device 有权非易失性存储器件和非易失性存储器件的数据写入方法公开(公告)号：US20060023509A1
公开(公告)日：2006-02-02
申请号：US11176324
申请日：2005-07-08
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A nonvolatile memory device, wherein each of memory cells includes one of nonvolatile memory elements and one of wordline switches, wherein each of the wordlines connects in common gate electrodes of the wordline switches of memory cells arranged in the row direction; wherein each of the bitlines connects in common the wordline switches of memory cells arranged in the column direction; and wherein one of the first control gate lines connects in common control gate electrodes of the nonvolatile memory elements of M memory cells in one of memory cell blocks (M is an integer equal to or greater than 2); and wherein, when writing data into a desired memory cell, the wordline switches of the memory cells are turned ON by applying a wordline write voltage to a wordlines corresponding to the desired memory cell, a bitline write voltage is applied to the bitlines connected to the memory cells, and a control gate line write voltage is applied to one of the first control gate lines disposed in the memory cell block.
摘要翻译： 一种非易失性存储器件，其中每个存储器单元包括非易失性存储器元件和字线开关中的一个，其中每个字线连接在沿行方向布置的存储器单元的字线开关的公共栅电极中; 其中每个位线共同地连接在列方向上布置的存储器单元的字线开关; 并且其中一个第一控制栅极线连接在存储单元块之一中的M个存储单元的非易失性存储元件的公共控制栅极中（M为等于或大于2的整数）; 并且其中当将数据写入期望的存储单元时，通过将字线写入电压施加到对应于期望的存储单元的字线来使存储单元的字线切换为ON，位线写入电压被施加到连接到所述存储单元的位线 存储单元和控制栅线写入电压被施加到设置在存储单元块中的第一控制栅极线之一。
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公开(公告)号：US20050275009A1
公开(公告)日：2005-12-15
申请号：US11148302
申请日：2005-06-09
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28273 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/7883
摘要： A nonvolatile memory device includes: a semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer; a semiconductor section of a second conductivity type provided in the first region and functioning as a control gate; a semiconductor section of the first conductivity type provided in the second region; a semiconductor section of the second conductivity type provided in the third region; an insulating layer provided on the semiconductor layer in the first to third regions; a floating gate electrode provided on the insulating layer across the first to third regions; impurity regions of the first conductivity type provided on each side of the floating gate electrode in the first region; impurity regions of the second conductivity type provided on each side of the floating gate electrode in the second region and functioning as either a source region or a drain region; and impurity regions of the first conductivity type provided on each side of the floating gate electrode in the third region and functioning as either a source region or a drain region.
摘要翻译： 非易失性存储器件包括：第一导电类型的半导体层，其中第一区域，第二区域和第三区域被隔离绝缘层分隔; 第二导电类型的半导体部分，设置在第一区域中并用作控制栅极; 设置在第二区域中的第一导电类型的半导体部分; 设置在第三区域中的第二导电类型的半导体部分; 设置在第一至第三区域的半导体层上的绝缘层; 在第一至第三区域上设置在绝缘层上的浮栅电极; 设置在第一区域中的浮置栅电极的每一侧上的第一导电类型的杂质区域; 第二导电类型的杂质区域设置在第二区域中的浮置栅电极的每一侧上并且用作源极区域或漏极区域; 以及设置在第三区域中的浮栅的每一侧上的第一导电类型的杂质区，并且用作源区或漏区。
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公开(公告)号：US06594186B2
公开(公告)日：2003-07-15
申请号：US10171421
申请日：2002-06-12
IPC分类号： G11C2900
摘要： A semiconductor memory having a plurality of memory cells includes a first terminal that becomes a power supply terminal for the semiconductor memory, a second terminal that becomes a ground terminal for the semiconductor memory, a third terminal for inputting a burn-in mode signal to place the semiconductor memory in a burn-in mode and a fourth terminal for inputting an external clock signal. The semiconductor memory further includes an address signal generation section that generates an address signal for selecting each of the plurality of memory cells based on counting of the clock signal while the burn-in mode signal is input. A data signal generation section generates a data signal based on the clock signal while the burn-in mode signal is input. A data writing section writes data of the data signal in the memory cells selected by the address signal.
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公开(公告)号：US20120019566A1
公开(公告)日：2012-01-26
申请号：US13137995
申请日：2011-09-23
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G09G5/10
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译： 集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域， 在第一至第N电路块CB1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。
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公开(公告)号：US08054710B2
公开(公告)日：2011-11-08
申请号：US11477670
申请日：2006-06-30
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G11C8/00
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译： 集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域， 在第一至第N电路块CB1至CBN的D4侧。 使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。 使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。
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