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    Back-sampling analog to digital converter
    1.
    发明授权
    Back-sampling analog to digital converter 失效
    反向采样模数转换器

    公开(公告)号：US5059982A

    公开(公告)日：1991-10-22

    申请号：US587089

    申请日：1990-09-24

    申请人： Kantilal Bacrania ,  Chong I. Chi

    发明人： Kantilal Bacrania ,  Chong I. Chi

    IPC分类号： H03M1/08 ,  H03M1/46 ,  H03M1/80

    CPC分类号： H03M1/0836 ,  H03M1/466 ,  H03M1/804

    摘要： Analog to digital conversion begins by terminating the acquisition phase of the analog input signal and immediately starting the successive approximation conversion phase upon receipt of a start conversion command. Upon the completion of the successive approximation conversion phase and latching the result, the array is rest if required. The comparator offset is sampled-and-held, if required, and the acquisition phase is initiated and continues until the receipt or occurrence of the next start conversion command.

    摘要翻译： 模拟数字转换通过终止模拟输入信号的采集阶段开始，并在接收到开始转换命令后立即开始逐次逼近转换阶段。 在逐次逼近转换阶段完成并锁存结果后，如果需要，阵列就会休息。 如果需要，比较器偏移被采样保持，并且采集阶段被启动并继续，直到接收或发生下一个启动转换命令。

    Analog-to-digital converter and method of fabrication
    2.
    发明授权
    Analog-to-digital converter and method of fabrication 失效
    模数转换器和制造方法

    公开(公告)号：US5369309A

    公开(公告)日：1994-11-29

    申请号：US785325

    申请日：1991-10-30

    申请人： Kantilal Bacrania ,  Chong I. Chi ,  Gregory J. Fisher

    发明人： Kantilal Bacrania ,  Chong I. Chi ,  Gregory J. Fisher

    IPC分类号： G05F3/26 ,  G05F3/30 ,  G11C27/02 ,  H01L27/02 ,  H01L27/06 ,  H03F1/52 ,  H03F3/50 ,  H03G1/00 ,  H03K5/15 ,  H03K17/22 ,  H03M1/16 ,  H03M1/36 ,  H03M1/00

    CPC分类号： H03G1/0082 ,  G05F3/262 ,  G05F3/30 ,  G11C27/026 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0688 ,  H03F1/523 ,  H03F3/505 ,  H03K17/223 ,  H03K5/15 ,  H03M1/162 ,  H03F2200/294 ,  H03M1/365

    摘要： A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog converter for low noise operation. CMOS digital error correction and BiCMOS output drivers provide high packing density plus large output load handling. Timing control aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

    摘要翻译： 两步模拟 - 数字转换器和BiCMOS制造方法。 该制造方法提供了数字CMOS器件与模拟器件的伪衬底隔离。 转换器在闪存模数转换器和数模转换器中使用NPN电流切换，以实现低噪声运行。 CMOS数字纠错和BiCMOS输出驱动器提供高封装密度和大输出负载处理。 定时控制聚合切换事件，并在噪声敏感操作无效时将其置于间隔。 该制造方法使用具有有限热处理的薄外延层来为NPN和PNP器件提供大的击穿和早期电压。 激光修整电阻器由于在底层BPSG和低氮化氢钝化中的掺杂剂稳定性而提供较小的长期漂移。

    Back-sampling charge redistribution analog to digital converter
    4.
    发明授权
    Back-sampling charge redistribution analog to digital converter 失效
    反向采样电荷再分配模数转换器

    公开(公告)号：US4982194A

    公开(公告)日：1991-01-01

    申请号：US340705

    申请日：1989-04-20

    申请人： Kantilal Bacrania ,  Chong I. Chi

    发明人： Kantilal Bacrania ,  Chong I. Chi

    IPC分类号： H03M1/08 ,  H03M1/46 ,  H03M1/80

    CPC分类号： H03M1/0836 ,  H03M1/468 ,  H03M1/804

    摘要： Aperture delay and jitter are reduced when the sequence of operation of a charge redistribution analog to digital converter is arranged so that signal acquisition occurs in the idle time of the converter. Conversion begins by terminating the acquisition or sample phase immediately upon receipt of the start conversion command. Approximation begins directly thereafter. Upon completion of the successive approximation conversion phase and latching the result the capacitor array is discharged. The comparator offset is sampled and held and the acquisition phase is initiated and continues until receipt or occurrence of the next start conversion command.

    摘要翻译： 当电荷重分配模数转换器的工作顺序被布置成使得信号采集发生在转换器的空闲时间时，孔径延迟和抖动减小。 转换开始于接收到开始转换命令后立即终止采集或采样阶段。 之后直接开始。 在完成逐次逼近转换阶段并锁存结果后，电容器阵列被放电。 比较器偏移被采样和保持，并且采集阶段被启动并继续，直到接收或发生下一个启动转换命令。

    Statistically based current generator circuit
    5.
    发明授权
    Statistically based current generator circuit 失效
    基于统计的电流发生器电路

    公开(公告)号：US5701097A

    公开(公告)日：1997-12-23

    申请号：US515435

    申请日：1995-08-15

    申请人： Gregory J. Fisher ,  Chong I. Chi

    发明人： Gregory J. Fisher ,  Chong I. Chi

    IPC分类号： G05F3/26 ,  H03K17/14

    CPC分类号： G05F3/267

    摘要： The invention is a circuit and method for selecting a plurality of different types of resisters and for reliably manufacturing a current generator across different wafer lots. In one embodiment, a monolithic current generator applies the output voltage of a voltage reference circuit across a plurality of series-connected resisters of different types. The resisters are preferably statistically independent resisters, which permits a total resistance with a predefined standard resistance deviation across manufacturing wafer lots. An output current may then be produced which has a predefined standard current deviation across manufacturing wafer lots. In a preferred embodiment, no more than six different types of resisters are used. The resisters may be chosen from the group consisting of diffused resisters, implanted resisters, thin film resisters, metal resisters, and composite resisters. The present invention also includes a method for reliably producing current generators across wafer lots. A plurality of voltage reference circuits are formed in electrical connection with a plurality of n different types of series-connected resisters in a plurality of semiconductor die. Preferably, the plurality of n statistically independent resisters are formed with each resistor of the plurality of statistically independent resisters having a predefined standard resistance deviation across manufacturing wafer lots. An output voltage from respective ones of the voltage reference circuits applied across respective ones of the plurality of n different types of resisters would produce a plurality of respective output currents. Each of the respective output currents preferably has a predefined standard current deviation across manufacturing wafer lots.

    摘要翻译： 本发明是用于选择多种不同类型的电阻并且用于在不同的晶片批次之间可靠地制造电流发生器的电路和方法。 在一个实施例中，单片电流发生器跨越不同类型的多个串联电阻器施加电压参考电路的输出电压。 电阻器优选地是统计学上独立的电阻器，其允许在制造晶片批次处具有预定义的标准电阻偏差的总电阻。 然后可以产生输出电流，其在制造晶圆批次之间具有预定义的标准电流偏差。 在优选实施例中，不超过六种不同类型的电阻器被使用。 电阻器可以选自由扩散电阻器，植入电阻器，薄膜电阻器，金属电阻器和复合电阻器组成的组。 本发明还包括一种用于在晶片批次之间可靠地生产电流发生器的方法。 多个电压参考电路形成为与多个半导体管芯中的多个n种不同类型的串联电阻器电连接。 优选地，多个统计学上独立的电阻器形成，所述多个统计独立电阻器中的每个电阻器具有跨制造晶片批次的预定标准电阻偏差。 来自施加在多个n种不同类型的电阻器中的相应电阻器上的各个电压参考电路的输出电压将产生多个相应的输出电流。 各个输出电流中的每一个优选地跨制造晶圆批次具有预定义的标准电流偏差。