Wear leveling techniques for flash EEPROM systems
    2.
    发明授权
    Wear leveling techniques for flash EEPROM systems 失效
    闪存EEPROM系统的磨损均衡技术

    公开(公告)号:US07353325B2

    公开(公告)日:2008-04-01

    申请号:US11028882

    申请日:2005-01-03

    IPC分类号: G06F12/02

    摘要: A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

    摘要翻译: 由闪存电可擦除和可编程只读存储器(“EEPROM”)组成的块的大容量存储系统被组合成块,这些块又被分组到存储体中,以便管理存储器经历的擦除和重写周期的数量 银行为了延长内存系统的使用寿命。 由于这种类型的存储器单元在有限数量的擦除和重写周期之后变得不可用,尽管在数万个周期中,避免了不均匀地使用存储器组,使得整个存储器不会变得不起作用,因为它的一个存储体具有 达到了终点,而其他银行也没有被使用。 监视存储器组的相对使用,并且响应于不均匀使用的检测,使它们的物理地址彼此周期性交换,以便在存储器的使用寿命期内甚至使用它们。

    Wear leveling techniques for flash EEPROM systems

    公开(公告)号:US06594183B1

    公开(公告)日:2003-07-15

    申请号:US09108084

    申请日:1998-06-30

    IPC分类号: G11C1604

    摘要: A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

    Wear leveling techniques for flash EEPROM systems
    4.
    发明授权
    Wear leveling techniques for flash EEPROM systems 失效
    闪存EEPROM系统的磨损均衡技术

    公开(公告)号:US06850443B2

    公开(公告)日:2005-02-01

    申请号:US10428422

    申请日:2003-05-02

    IPC分类号: G11C8/12 G11C16/34 G11C11/00

    摘要: A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

    摘要翻译: 由闪存电可擦除和可编程只读存储器(“EEPROM”)组成的块的大容量存储系统被组合成块,这些块又被分组到存储体中,以便管理存储器经历的擦除和重写周期的数量 银行为了延长内存系统的使用寿命。 由于这种类型的存储器单元在有限数量的擦除和重写周期之后变得不可用,尽管在数万个周期中,避免了不均匀地使用存储器组,使得整个存储器不会变得不起作用,因为它的一个存储体具有 达到了终点,而其他银行也没有被使用。 监视存储器组的相对使用,并且响应于不均匀使用的检测,使它们的物理地址彼此周期性交换,以便在存储器的使用寿命期内甚至使用它们。

    Wear leveling techniques for flash EEPROM systems
    5.
    发明授权
    Wear leveling techniques for flash EEPROM systems 失效
    闪存EEPROM系统的磨损均衡技术

    公开(公告)号:US06230233B1

    公开(公告)日:2001-05-08

    申请号:US07759212

    申请日:1991-09-13

    IPC分类号: G06F1202

    摘要: A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

    摘要翻译: 由闪存电可擦除和可编程只读存储器(“EEPROM”)组成的块的大容量存储系统被组合成块,这些块又被分组到存储体中,以便管理存储器经历的擦除和重写周期的数量 银行为了延长内存系统的使用寿命。 由于这种类型的存储器单元在有限数量的擦除和重写周期之后变得不可用,尽管在数万个周期中,避免了不均匀地使用存储器组,使得整个存储器不会变得不起作用,因为它的一个存储体具有 达到了终点,而其他银行也没有被使用。 监视存储器组的相对使用,并且响应于不均匀使用的检测,使它们的物理地址彼此周期性交换,以便在存储器的使用寿命期内甚至使用它们。

    Device and method for controlling solid-state memory system
    6.
    发明授权
    Device and method for controlling solid-state memory system 失效
    用于控制固态存储器系统的装置和方法

    公开(公告)号:US08125834B2

    公开(公告)日:2012-02-28

    申请号:US12619581

    申请日:2009-11-16

    IPC分类号: G11C16/04 G06F13/00

    摘要: A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

    摘要翻译: 存储器系统包括固态存储器件的阵列,其经由具有极少线的器件总线与控制器模块通信并处于控制器模块的控制之下。 这形成了集成电路大容量存储系统,其被设想来替代大容量存储系统,例如计算机系统中的磁盘驱动器存储器。 命令,地址和数据信息被串行化为组件字符串,并在控制器模块和存储器件阵列之间传输之前被多路复用。 串行化信息伴随着一个控制信号,以帮助整理复用的组件。 阵列中的每个存储器件都安装在多位安装上,并通过阵列安装分配阵列地址。 通过在设备总线上广播的适当地址来选择存储器件,而不需要通常的专用选择信号。 使用保留阵列特定安装多位配置来无条件地选择安装在其上的装置。 通过设备总线广播的保留的预定义地址取消选择所有先前选择的存储设备。 读取性能通过读取流技术得到增强,其中当当前块的数据被序列化并从存储器子系统设备移出到控制器模块时,控制器模块还设置下一个数据块开始的地址 寻址内存系统。

    Device and Method for Controlling Solid-State Memory System
    7.
    发明申请
    Device and Method for Controlling Solid-State Memory System 失效
    用于控制固态存储器系统的装置和方法

    公开(公告)号:US20100064098A1

    公开(公告)日:2010-03-11

    申请号:US12619581

    申请日:2009-11-16

    IPC分类号: G06F12/00 G06F12/02

    摘要: A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

    摘要翻译: 存储器系统包括固态存储器件的阵列,其经由具有极少线的器件总线与控制器模块通信并处于控制器模块的控制之下。 这形成了集成电路大容量存储系统,其被设想来替代大容量存储系统,例如计算机系统中的磁盘驱动器存储器。 命令,地址和数据信息被串行化为组件字符串,并在控制器模块和存储器件阵列之间传输之前被多路复用。 串行化信息伴随着一个控制信号,以帮助整理复用的组件。 阵列中的每个存储器件都安装在多位安装上,并通过阵列安装分配阵列地址。 通过在设备总线上广播的适当地址来选择存储器件,而不需要通常的专用选择信号。 使用保留阵列特定安装多位配置来无条件地选择安装在其上的装置。 通过设备总线广播的保留的预定义地址取消选择所有先前选择的存储设备。 读取性能通过读取流技术得到增强,其中当当前块的数据被序列化并从存储器子系统设备移出到控制器模块时,控制器模块还设置下一个数据块开始的地址 寻址内存系统。

    Solid state memory system including plural memory chips and a serialized
bus
    9.
    发明授权
    Solid state memory system including plural memory chips and a serialized bus 失效
    包括多个存储器芯片和串行总线的固态存储器系统

    公开(公告)号:US5430859A

    公开(公告)日:1995-07-04

    申请号:US736733

    申请日:1991-07-26

    摘要: A memory system includes an array of solid-state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit and assigned an array address. A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A particular multi-bit mount configuration is used to unconditionally select the device mounted thereon. A predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

    摘要翻译: 存储器系统包括固态存储器件的阵列,其经由具有极少线的器件总线与控制器模块通信并处于控制器模块的控制之下。 这形成了集成电路大容量存储系统,其被设想来替代大容量存储系统,例如计算机系统中的磁盘驱动器存储器。 命令,地址和数据信息被串行化为组件字符串,并在控制器模块和存储器件阵列之间传输之前被多路复用。 序列化信息伴随着一个控制信号,以帮助整理复用的组件。 阵列中的每个存储器件都安装在多位并分配了一个阵列地址。 通过在设备总线上广播的适当地址来选择存储设备,而不需要通常的专用选择信号。 使用特定的多位安装配置来无条件地选择安装在其上的设备。 通过设备总线广播的预定义地址将取消所有先前选择的存储设备。 通过读取流技术增强读取性能,其中当当前块的数据被串行化并从存储器件移出到控制器模块时,控制器模块还设置下一个数据块的地址以开始 寻址内存系统。

    Device and method for controlling solid-state memory system
    10.
    发明授权
    Device and method for controlling solid-state memory system 失效
    用于控制固态存储器系统的装置和方法

    公开(公告)号:US06317812B1

    公开(公告)日:2001-11-13

    申请号:US09657369

    申请日:2000-09-08

    IPC分类号: G06F1200

    摘要: A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted. A reserved address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

    摘要翻译: 存储器系统包括固态存储器件阵列,其经由具有极少线路的器件总线与控制器模块通信并处于控制器模块的控制之下。 这形成了集成电路大容量存储系统,其被设想来替代大容量存储系统,例如计算机系统中的磁盘驱动器存储器。 命令,地址和数据信息被串行化为组件字符串,并在控制器模块和存储器件阵列之间传输之前被多路复用。 序列化信息伴随着一个控制信号,以帮助整理复用的组件。 阵列中的每个内存设备都由阵列装载分配一个阵列地址。 通过在设备总线上广播的适当地址来选择存储设备,而不需要通常的专用选择信号。 保留阵列安装配置用于无条件地选择安装的设备。 通过设备总线广播的保留地址将取消所有先前选择的存储设备。 通过读取流技术增强读取性能,其中当当前大量数据被序列化并从存储器子系统移出到控制器模块时,控制器模块还设置下一个数据块的地址以开始 寻址内存系统。