公开(公告)号：US06720264B2

公开(公告)日：2004-04-13

申请号：US09749191

申请日：2000-12-26

申请人： Kashmir S. Sahota ,  Diana M. Schonauer ,  Johannes F. Groschopf ,  Gerd F. C. Marxsen ,  Steven C. Avanzino

发明人： Kashmir S. Sahota ,  Diana M. Schonauer ,  Johannes F. Groschopf ,  Gerd F. C. Marxsen ,  Steven C. Avanzino

IPC分类号： H01L21302

CPC分类号： C09K3/1463 ,  C09G1/02 ,  H01L21/3212

摘要： A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining. The organic additive is chosen from a class of compounds which form multiple strong adsorbant bonds to the surface of silica or copper, which provide a high degree of surface coverage onto the reactive species, thereby occupying potential reaction sites, and which are sized to sterically hinder the collisions between two reactant molecules which result in new bond formation. The organic additive-containing slurry cain be utilized throughout the entire polish time. Alternatively, a slurry not containing the organic additive can be utilized for a first portion of the polish, and a slurry containing the organic additive or a polishing solution containing the organic additive can be utilized for a second portion of the polish.

摘要翻译： 在铜金属化期间用于化学机械抛光（CMP）的Ta阻挡浆料包含抑制沉淀物形成和铜污染的有机添加剂。 有机添加剂选自一类化合物，其形成与二氧化硅或铜的表面的多个强吸附剂键，其在反应性物质上提供高度的表面覆盖度，从而占据潜在的反应位点，并且它们的大小适于空间阻碍 两个反应物分子之间的碰撞导致新的键形成。 在整个抛光时间内可以使用含有机添加剂的浆料。 或者，不含有机添加剂的浆料可用于抛光剂的第一部分，并且含有有机添加剂的浆料或含有有机添加剂的抛光溶液可用于第二部分抛光剂。

公开(公告)号：US06503418B2

公开(公告)日：2003-01-07

申请号：US09434146

申请日：1999-11-04

申请人： Kashmir S. Sahota ,  Diana M. Schonauer ,  Steven C. Avanzino

发明人： Kashmir S. Sahota ,  Diana M. Schonauer ,  Steven C. Avanzino

IPC分类号： C09K1300

CPC分类号： C09K3/1463

摘要： A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining. The organic additive is chosen from a class of compounds which form multiple strong adsorbant bonds to the surface of silica or copper, which provide a high degree of surface coverage onto the reactive species, thereby occupying potential reaction sites, and which are sized to sterically hinder the collisions between two reactant molecules which result in new bond formation

摘要翻译： 在铜金属化期间用于化学机械抛光（CMP）的Ta阻挡浆料包含抑制沉淀物形成和铜污染的有机添加剂。 有机添加剂选自一类化合物，其形成与二氧化硅或铜的表面的多个强吸附剂键，其在反应性物质上提供高度的表面覆盖度，从而占据潜在的反应位点，并且它们的大小适于空间阻碍 两个反应物分子之间的碰撞导致新的键形成

公开(公告)号：US06410443B1

公开(公告)日：2002-06-25

申请号：US09507810

申请日：2000-02-22

申请人： Steven C. Avanzino ,  Stephen Keetai Park ,  Kashmir S. Sahota ,  David H. Matsumoto ,  Mark Ramsbey

发明人： Steven C. Avanzino ,  Stephen Keetai Park ,  Kashmir S. Sahota ,  David H. Matsumoto ,  Mark Ramsbey

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/31053 ,  H01L2924/3011

摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemical-mechanical polishing (CMP) process with non-oxidizer containing slurry is used to selectively remove the ARC layer at a rate which is significantly faster than the removal rates of the dielectric layer or the tungsten contacts. Further, an ARC CMP buffing process is used with a soft buffing pad in the CMP process to buff the dielectric layer and tungsten contacts during the ARC layer removal.

摘要翻译： 本发明提供一种用于在基板表面上从电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨导电触头。 在一个实施例中，使用含有非氧化剂的浆料的化学 - 机械抛光（CMP）工艺以比电介质层或钨接触的去除速度显着更快的速率选择性地去除ARC层。 此外，ARC CMP抛光工艺与CMP抛光垫一起使用，以在ARC层去除期间抛光电介质层和钨触点。

公开(公告)号：US5665199A

公开(公告)日：1997-09-09

申请号：US493972

申请日：1995-06-23

申请人： Kashmir S. Sahota ,  Steven C. Avanzino

发明人： Kashmir S. Sahota ,  Steven C. Avanzino

IPC分类号： H01L21/3105 ,  H01L21/66 ,  H01L21/306

CPC分类号： H01L22/20 ,  H01L21/31053

摘要： A method for developing and characterizing a polish process for polishing an interlayer dielectric (ILD) layer for a specific product or a specific patterned metal layer is provided. A statistically-based model for ILD planarization by chemical mechanical polish (CMP) is used as a guide to determine, in an empirical manner, the proper amount of ILD polishing that will be required to planarize an ILD layer. The statistically-based model also shows the resulting ILD thicknesses to be expected. By relating the blank test wafer polished amount to the maximum amount of oxide removed from the field areas in the die and the total indicated range across the die, the ILD deposition thickness can be adjusted to attain the desired planarized ILD thickness. The attainment of local planarity, however, must be confirmed by an independent measurement technique. The polish process development methodology is extendible with respect to minimum interconnect feature size. This polish process development methodology can also be applied to products requiring multiple planarizations for multiple levels of interconnects.

摘要翻译： 提供了用于开发和表征用于抛光特定产品或特定图案化金属层的层间电介质（ILD）层的抛光工艺的方法。 通过化学机械抛光（CMP）的ILD平坦化的统计学模型被用作指导，以经验方式确定平面化ILD层所需的适当量的ILD抛光。 基于统计学的模型还显示了预期的ILD厚度。 通过将空白测试晶片抛光量与从模具中的场区域去除的氧化物的最大量和跨模具的总指示范围相关联，可以调节ILD沉积厚度以获得期望的平坦化ILD厚度。 然而，实现局部平面性必须通过独立的测量技术来确认。 抛光过程开发方法在最小互连特征尺寸方面是可扩展的。 这种抛光过程开发方法也可以应用于需要多层次互连的多平面化的产品。

公开(公告)号：US06699785B2

公开(公告)日：2004-03-02

申请号：US10375219

申请日：2003-02-26

申请人： Kai Yang ,  Kashmir S. Sahota ,  Steven C. Avanzino

发明人： Kai Yang ,  Kashmir S. Sahota ,  Steven C. Avanzino

IPC分类号： H01L214763

CPC分类号： H01L21/3212 ,  B24B7/228 ,  B24B21/04 ,  H01L21/7684

摘要： A manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the conductor core to the barrier layer in conjunction with a grooved polyurethane polish pad, a very thin barrier layer may be used without the conductor core and dielectric layer being subject to erosion and the conductor core being subject to dishing.

摘要翻译： 提供具有半导体器件的半导体衬底的制造方法。 在半导体衬底上形成器件电介质层。 器件电介质层上的沟道电介质层具有形成在其中的开口。 屏障层对通道开口进行排列。 导体芯填充阻挡层上的开口。 通过使用具有从导体芯到阻挡层的高选择性的抛光溶液与凹槽聚氨酯抛光垫结合，可以使用非常薄的阻挡层，而不会导体芯和介电层受到侵蚀，并且导体芯是 受到困扰。

公开(公告)号：US06184141B2

公开(公告)日：2001-02-06

申请号：US09198369

申请日：1998-11-24

申请人： Steven C. Avanzino ,  Kashmir S. Sahota ,  Gerd Marxsen

发明人： Steven C. Avanzino ,  Kashmir S. Sahota ,  Gerd Marxsen

IPC分类号： H01L2100

CPC分类号： H01L21/3212

摘要： A method of planarizing a copper containing conductive layer of a semiconductor wafer forms a blanketing copper containing layer within and upon a patterned substrate layer. Chemical mechanical polish (CMP) planarizing is performed on the copper containing layer at a relatively fast rate of removal until most of the layer is removed. The remaining portion of the layer is then CMP planarized at a second rate of removal, which is slower than the first rate of removal, until the copper containing layer is substantially completely removed and a barrier layer underlying the copper containing layer is reached. The multiple phase planarization of the copper containing layer avoids excessive dishing and pattern erosion while maintaining high throughput and uniform removal.

摘要翻译： 平面化半导体晶片的含铜导电层的方法在图案化的衬底层的内部和之上形成覆盖铜的层。 化学机械抛光（CMP）平面化在含铜层上以相对较快的去除速率进行，直到大部分层被去除。 然后将层的剩余部分以第二除去速率平坦化，其比第一脱除速率慢，直到基本上完全除去含铜层，并且到达含铜层下面的阻挡层。 含铜层的多相平面化避免了过度的凹陷和图案侵蚀，同时保持了高产量和均匀的去除。

公开(公告)号：US06413869B1

公开(公告)日：2002-07-02

申请号：US09877688

申请日：2001-06-08

申请人： Krishnashree Achuthan ,  Steven C. Avanzino ,  Kashmir S. Sahota

发明人： Krishnashree Achuthan ,  Steven C. Avanzino ,  Kashmir S. Sahota

IPC分类号： H01L21302

CPC分类号： H01L21/02074 ,  C09G1/02 ,  H01L21/3212 ,  H01L21/7684

摘要： A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and conductor core is deposited to fill the channel opening over the barrier layer. By using a polishing solution having a dielectric protective characteristic, chemical-mechanical polishing of the conductor core and the barrier layer with the surface of the dielectric layer stops at the surface of the dielectric layer after planarization.

摘要翻译： 提供了一种用于制造具有半导体器件的半导体衬底的集成电路的方法。 在半导体衬底上形成电介质层，并在电介质层中形成开口。 沉积阻挡层以对开口进行排列，并且沉积导体芯以填充阻挡层上的通道开口。 通过使用具有介电保护特性的抛光溶液，在平坦化之后，介电层表面的导体芯和阻挡层的化学机械抛光停止在介电层的表面。

公开(公告)号：US06177349B1

公开(公告)日：2001-01-23

申请号：US09206169

申请日：1998-12-07

申请人： Diana M. Schonauer ,  Steven C. Avanzino ,  Kai Yang

发明人： Diana M. Schonauer ,  Steven C. Avanzino ,  Kai Yang

IPC分类号： H01L2144

CPC分类号： H01L21/7684 ,  H01L21/76819

摘要： The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP by immersion in and/or double sided brush scrubbing with a chemical agent. Embodiments include removing controlled portions up to 50 Å of silicon oxide by immersion in and/or double sided brush scrubbing with a solution containing ammonium fluoride, diammonium hydrogen citrate, triammonium citrate, a surfactant and dionized water.

摘要翻译： 从Cu或Cu合金线发射到边界开放介质场中的枝晶的形成和/或生长通过从介电场中化学去除表面的一部分和CMP之后的线之间的浸入和/ 或用化学试剂双面刷洗。 实施例包括通过用含有氟化铵，柠檬酸氢铵，柠檬酸三铵，表面活性剂和二价离子水的溶液浸渍和/或双面刷洗来去除高达50埃的氧化硅的受控部分。

公开(公告)号：US6153933A

公开(公告)日：2000-11-28

申请号：US925821

申请日：1997-09-05

申请人： Darin A. Chan ,  Steven C. Avanzino ,  Subramanian Venkatkrishnan ,  Minh Van Ngo ,  Christy Mei-Chu Woo de la Girond'arc ,  Diana M. Schonauer

发明人： Darin A. Chan ,  Steven C. Avanzino ,  Subramanian Venkatkrishnan ,  Minh Van Ngo ,  Christy Mei-Chu Woo de la Girond'arc ,  Diana M. Schonauer

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76819 ,  H01L23/5329 ,  H01L2924/0002

摘要： A multiple-layer interconnect structure in an integrated circuit, is formed using damascene techniques. A first layer interconnect has a first dielectric layer through which at least one first layer conductor extends. A second layer interconnect is then formed on the first layer interconnect. The second layer interconnect also includes a second layer dielectric through which at least one second layer conductor extends. However, the second layer interconnect is created by first forming a thick second later dielectric layer and then reducing the thickness of the second layer dielectric prior to a patterning step. As a result topographical irregularities that may have carried over to the second layer interconnect from the first layer interconnect are removed by providing a substantially planar surface on the second layer dielectric.

摘要翻译： 使用镶嵌技术形成集成电路中的多层互连结构。 第一层互连具有第一介电层，至少一个第一层导体通过第一介电层延伸。 然后在第一层互连上形成第二层互连。 第二层互连还包括第二层电介质，至少一层第二层导体延伸穿过第二层电介质。 然而，第二层互连通过首先形成厚的第二次介质层，然后在图案化步骤之前减小第二层电介质的厚度而产生。 因此，可以通过在第二层电介质上提供基本平坦的表面来去除可能已经承载到来自第一层互连的第二层互连的拓扑不规则。

公开(公告)号：US06207569B1

公开(公告)日：2001-03-27

申请号：US09206163

申请日：1998-12-07

申请人： Diana M. Schonauer ,  Steven C. Avanzino ,  Kai Yang

发明人： Diana M. Schonauer ,  Steven C. Avanzino ,  Kai Yang

IPC分类号： H01L21302

CPC分类号： H01L21/7684 ,  H01L21/02074 ,  H01L21/3212

摘要： The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP with a solution comprising HF and H2O. Embodiments include removing up to 50 Å of silicon oxide by treating the wafer in a spray acid processor with a solution containing HF and deionized water at a water to acid ratio of about 100:1 to about 250:1.

摘要翻译： 通过用包含HF的溶液通过化学去除表面的一部分从电介质场和CMP之后的线之间，从Cu或Cu合金线发射到边界开放电介质场中的枝晶的形成和/或生长被抑制或显着减少 和H2O。 实施方案包括通过在喷雾酸处理器中用含有HF和去离子水的溶液以大约100:1至大约250:1的水与酸比例处理晶片去除多达50的氧化硅。