公开(公告)号：US06410443B1

公开(公告)日：2002-06-25

申请号：US09507810

申请日：2000-02-22

申请人： Steven C. Avanzino ,  Stephen Keetai Park ,  Kashmir S. Sahota ,  David H. Matsumoto ,  Mark Ramsbey

发明人： Steven C. Avanzino ,  Stephen Keetai Park ,  Kashmir S. Sahota ,  David H. Matsumoto ,  Mark Ramsbey

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/31053 ,  H01L2924/3011

摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemical-mechanical polishing (CMP) process with non-oxidizer containing slurry is used to selectively remove the ARC layer at a rate which is significantly faster than the removal rates of the dielectric layer or the tungsten contacts. Further, an ARC CMP buffing process is used with a soft buffing pad in the CMP process to buff the dielectric layer and tungsten contacts during the ARC layer removal.

摘要翻译： 本发明提供一种用于在基板表面上从电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨导电触头。 在一个实施例中，使用含有非氧化剂的浆料的化学 - 机械抛光（CMP）工艺以比电介质层或钨接触的去除速度显着更快的速率选择性地去除ARC层。 此外，ARC CMP抛光工艺与CMP抛光垫一起使用，以在ARC层去除期间抛光电介质层和钨触点。

公开(公告)号：US06720264B2

公开(公告)日：2004-04-13

申请号：US09749191

申请日：2000-12-26

申请人： Kashmir S. Sahota ,  Diana M. Schonauer ,  Johannes F. Groschopf ,  Gerd F. C. Marxsen ,  Steven C. Avanzino

发明人： Kashmir S. Sahota ,  Diana M. Schonauer ,  Johannes F. Groschopf ,  Gerd F. C. Marxsen ,  Steven C. Avanzino

IPC分类号： H01L21302

CPC分类号： C09K3/1463 ,  C09G1/02 ,  H01L21/3212

摘要： A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining. The organic additive is chosen from a class of compounds which form multiple strong adsorbant bonds to the surface of silica or copper, which provide a high degree of surface coverage onto the reactive species, thereby occupying potential reaction sites, and which are sized to sterically hinder the collisions between two reactant molecules which result in new bond formation. The organic additive-containing slurry cain be utilized throughout the entire polish time. Alternatively, a slurry not containing the organic additive can be utilized for a first portion of the polish, and a slurry containing the organic additive or a polishing solution containing the organic additive can be utilized for a second portion of the polish.

摘要翻译： 在铜金属化期间用于化学机械抛光（CMP）的Ta阻挡浆料包含抑制沉淀物形成和铜污染的有机添加剂。 有机添加剂选自一类化合物，其形成与二氧化硅或铜的表面的多个强吸附剂键，其在反应性物质上提供高度的表面覆盖度，从而占据潜在的反应位点，并且它们的大小适于空间阻碍 两个反应物分子之间的碰撞导致新的键形成。 在整个抛光时间内可以使用含有机添加剂的浆料。 或者，不含有机添加剂的浆料可用于抛光剂的第一部分，并且含有有机添加剂的浆料或含有有机添加剂的抛光溶液可用于第二部分抛光剂。

公开(公告)号：US5665199A

公开(公告)日：1997-09-09

申请号：US493972

申请日：1995-06-23

申请人： Kashmir S. Sahota ,  Steven C. Avanzino

发明人： Kashmir S. Sahota ,  Steven C. Avanzino

IPC分类号： H01L21/3105 ,  H01L21/66 ,  H01L21/306

CPC分类号： H01L22/20 ,  H01L21/31053

摘要： A method for developing and characterizing a polish process for polishing an interlayer dielectric (ILD) layer for a specific product or a specific patterned metal layer is provided. A statistically-based model for ILD planarization by chemical mechanical polish (CMP) is used as a guide to determine, in an empirical manner, the proper amount of ILD polishing that will be required to planarize an ILD layer. The statistically-based model also shows the resulting ILD thicknesses to be expected. By relating the blank test wafer polished amount to the maximum amount of oxide removed from the field areas in the die and the total indicated range across the die, the ILD deposition thickness can be adjusted to attain the desired planarized ILD thickness. The attainment of local planarity, however, must be confirmed by an independent measurement technique. The polish process development methodology is extendible with respect to minimum interconnect feature size. This polish process development methodology can also be applied to products requiring multiple planarizations for multiple levels of interconnects.

摘要翻译： 提供了用于开发和表征用于抛光特定产品或特定图案化金属层的层间电介质（ILD）层的抛光工艺的方法。 通过化学机械抛光（CMP）的ILD平坦化的统计学模型被用作指导，以经验方式确定平面化ILD层所需的适当量的ILD抛光。 基于统计学的模型还显示了预期的ILD厚度。 通过将空白测试晶片抛光量与从模具中的场区域去除的氧化物的最大量和跨模具的总指示范围相关联，可以调节ILD沉积厚度以获得期望的平坦化ILD厚度。 然而，实现局部平面性必须通过独立的测量技术来确认。 抛光过程开发方法在最小互连特征尺寸方面是可扩展的。 这种抛光过程开发方法也可以应用于需要多层次互连的多平面化的产品。

公开(公告)号：US06699785B2

公开(公告)日：2004-03-02

申请号：US10375219

申请日：2003-02-26

申请人： Kai Yang ,  Kashmir S. Sahota ,  Steven C. Avanzino

发明人： Kai Yang ,  Kashmir S. Sahota ,  Steven C. Avanzino

IPC分类号： H01L214763

CPC分类号： H01L21/3212 ,  B24B7/228 ,  B24B21/04 ,  H01L21/7684

摘要： A manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the conductor core to the barrier layer in conjunction with a grooved polyurethane polish pad, a very thin barrier layer may be used without the conductor core and dielectric layer being subject to erosion and the conductor core being subject to dishing.

摘要翻译： 提供具有半导体器件的半导体衬底的制造方法。 在半导体衬底上形成器件电介质层。 器件电介质层上的沟道电介质层具有形成在其中的开口。 屏障层对通道开口进行排列。 导体芯填充阻挡层上的开口。 通过使用具有从导体芯到阻挡层的高选择性的抛光溶液与凹槽聚氨酯抛光垫结合，可以使用非常薄的阻挡层，而不会导体芯和介电层受到侵蚀，并且导体芯是 受到困扰。

公开(公告)号：US06184141B2

公开(公告)日：2001-02-06

申请号：US09198369

申请日：1998-11-24

申请人： Steven C. Avanzino ,  Kashmir S. Sahota ,  Gerd Marxsen

发明人： Steven C. Avanzino ,  Kashmir S. Sahota ,  Gerd Marxsen

IPC分类号： H01L2100

CPC分类号： H01L21/3212

摘要： A method of planarizing a copper containing conductive layer of a semiconductor wafer forms a blanketing copper containing layer within and upon a patterned substrate layer. Chemical mechanical polish (CMP) planarizing is performed on the copper containing layer at a relatively fast rate of removal until most of the layer is removed. The remaining portion of the layer is then CMP planarized at a second rate of removal, which is slower than the first rate of removal, until the copper containing layer is substantially completely removed and a barrier layer underlying the copper containing layer is reached. The multiple phase planarization of the copper containing layer avoids excessive dishing and pattern erosion while maintaining high throughput and uniform removal.

摘要翻译： 平面化半导体晶片的含铜导电层的方法在图案化的衬底层的内部和之上形成覆盖铜的层。 化学机械抛光（CMP）平面化在含铜层上以相对较快的去除速率进行，直到大部分层被去除。 然后将层的剩余部分以第二除去速率平坦化，其比第一脱除速率慢，直到基本上完全除去含铜层，并且到达含铜层下面的阻挡层。 含铜层的多相平面化避免了过度的凹陷和图案侵蚀，同时保持了高产量和均匀的去除。

公开(公告)号：US06503418B2

公开(公告)日：2003-01-07

申请号：US09434146

申请日：1999-11-04

申请人： Kashmir S. Sahota ,  Diana M. Schonauer ,  Steven C. Avanzino

发明人： Kashmir S. Sahota ,  Diana M. Schonauer ,  Steven C. Avanzino

IPC分类号： C09K1300

CPC分类号： C09K3/1463

摘要： A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining. The organic additive is chosen from a class of compounds which form multiple strong adsorbant bonds to the surface of silica or copper, which provide a high degree of surface coverage onto the reactive species, thereby occupying potential reaction sites, and which are sized to sterically hinder the collisions between two reactant molecules which result in new bond formation

摘要翻译： 在铜金属化期间用于化学机械抛光（CMP）的Ta阻挡浆料包含抑制沉淀物形成和铜污染的有机添加剂。 有机添加剂选自一类化合物，其形成与二氧化硅或铜的表面的多个强吸附剂键，其在反应性物质上提供高度的表面覆盖度，从而占据潜在的反应位点，并且它们的大小适于空间阻碍 两个反应物分子之间的碰撞导致新的键形成

公开(公告)号：US06413869B1

公开(公告)日：2002-07-02

申请号：US09877688

申请日：2001-06-08

申请人： Krishnashree Achuthan ,  Steven C. Avanzino ,  Kashmir S. Sahota

发明人： Krishnashree Achuthan ,  Steven C. Avanzino ,  Kashmir S. Sahota

IPC分类号： H01L21302

CPC分类号： H01L21/02074 ,  C09G1/02 ,  H01L21/3212 ,  H01L21/7684

摘要： A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and conductor core is deposited to fill the channel opening over the barrier layer. By using a polishing solution having a dielectric protective characteristic, chemical-mechanical polishing of the conductor core and the barrier layer with the surface of the dielectric layer stops at the surface of the dielectric layer after planarization.

摘要翻译： 提供了一种用于制造具有半导体器件的半导体衬底的集成电路的方法。 在半导体衬底上形成电介质层，并在电介质层中形成开口。 沉积阻挡层以对开口进行排列，并且沉积导体芯以填充阻挡层上的通道开口。 通过使用具有介电保护特性的抛光溶液，在平坦化之后，介电层表面的导体芯和阻挡层的化学机械抛光停止在介电层的表面。

公开(公告)号：US06426297B1

公开(公告)日：2002-07-30

申请号：US09905296

申请日：2001-07-13

申请人： Kashmir S. Sahota ,  Krishnashree Achuthan ,  Sergey D. Lopatin

发明人： Kashmir S. Sahota ,  Krishnashree Achuthan ,  Sergey D. Lopatin

IPC分类号： H01L21382

CPC分类号： H01L21/7684 ,  B24B37/042 ,  B24B49/16 ,  H01L21/3212

摘要： A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor wafer and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and a conductor core is deposited to fill the channel opening over the barrier layer. The semiconductor wafer is then subjected to chemical-mechanical polishing using a differential pressure between the center of the semiconductor wafer and its periphery.

摘要翻译： 提供了一种用于制造具有半导体器件的半导体衬底的集成电路的方法。 在半导体晶片上形成电介质层，并在电介质层中形成开口。 沉积阻挡层以对开口进行排列，并且沉积导体芯以填充阻挡层上的通道开口。 然后使用半导体晶片的中心与其周边之间的压差对半导体晶片进行化学机械抛光。

公开(公告)号：US5923993A

公开(公告)日：1999-07-13

申请号：US982230

申请日：1997-12-17

申请人： Kashmir S. Sahota

发明人： Kashmir S. Sahota

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229 ,  Y10S148/05

摘要： A fabrication process for manufacturing integrated circuits with isolation trenches. The process includes the use of two nitride layers and an oxide layer formed by high density plasma oxidation, to provide isolation trenches free of dishing. The isolated regions are useable for fabrication microelectronic circuit devices, such as MOS transistors or flash memory devices.

摘要翻译： 用于制造具有隔离沟槽的集成电路的制造工艺。 该方法包括使用两个氮化物层和通过高密度等离子体氧化形成的氧化物层，以提供没有凹陷的隔离沟槽。 隔离区域可用于制造微电子电路器件，例如MOS晶体管或闪存器件。

公开(公告)号：US07208382B1

公开(公告)日：2007-04-24

申请号：US10151595

申请日：2002-05-16

申请人： Jeffrey P. Erhardt ,  Kashmir S. Sahota ,  Emmanuil Lingunis ,  Nga-Ching Wong

发明人： Jeffrey P. Erhardt ,  Kashmir S. Sahota ,  Emmanuil Lingunis ,  Nga-Ching Wong

IPC分类号： H01L21/04

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/66621 ,  H01L29/66636

摘要： A method and structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in the opening. A structure is over the doped high conductivity region selected from a group consisting of a wordline, a gate, a dielectric layer, and a combination thereof.

摘要翻译： 提供了一种具有其中设置有开口的半导体衬底的集成电路的方法和结构。 掺杂的高导电性区域由开口中的掺杂材料和靠近开口中的掺杂材料的扩散掺杂区形成。 结构在从由字线，栅极，电介质层及其组合组成的组中选择的掺杂高导电率区域之上。