公开(公告)号：US20060261914A1

公开(公告)日：2006-11-23

申请号：US11414261

申请日：2006-05-01

申请人： Katsunari Moriai ,  Dai Matsuoka ,  Takahiro Sato

发明人： Katsunari Moriai ,  Dai Matsuoka ,  Takahiro Sato

IPC分类号： H03H7/01

CPC分类号： H01C7/1006 ,  H01C7/18 ,  H01C13/02 ,  H01F27/40 ,  H01F2017/0026 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1758 ,  H03H2001/0085

摘要： An object of the present invention is to provide a multilayer filter constructed so as to be less likely to suffer peeling between a varistor part and an inductor part. A multilayer filter 10 as a preferred embodiment has a structure in which a varistor part 20 and an inductor part are stacked. The varistor part 30 consists of a stack of varistor layers 31, 32 with internal electrodes 31a, 32a, and the varistor layers contain ZnO as a principal component, and contain at least one element selected from the group consisting of Pr and Bi, Co, and Al as additives. The inductor part 20 consists of a stack of inductor layers 21-24 with conductor patterns 21a-24a, and the inductor layers contain ZnO as a principal component and substantially contain neither Co nor Al.

摘要翻译： 本发明的目的是提供一种构造成不可能在变阻器部分和电感器部分之间发生剥离的多层滤波器。 作为优选实施例的多层滤波器10具有其中堆叠有变阻器部件20和电感器部件的结构。 变阻器部分30由一组具有内部电极31a，32a的可变电阻层31,32组成，并且变阻器层含有ZnO作为主要成分，并含有选自Pr和Bi中的至少一种元素， Co和Al作为添加剂。 电感器部分20由具有导体图案21a-24a的电感器层21-24的叠层组成，并且电感器层包含ZnO作为主要成分并且基本上不含Co和Al。

公开(公告)号：US07652554B2

公开(公告)日：2010-01-26

申请号：US11414261

申请日：2006-05-01

申请人： Katsunari Moriai ,  Dai Matsuoka ,  Takahiro Sato

发明人： Katsunari Moriai ,  Dai Matsuoka ,  Takahiro Sato

IPC分类号： H01C7/00

CPC分类号： H01C7/1006 ,  H01C7/18 ,  H01C13/02 ,  H01F27/40 ,  H01F2017/0026 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1758 ,  H03H2001/0085

摘要： An object of the present invention is to provide a multilayer filter constructed so as to be less likely to suffer peeling between a varistor part and an inductor part. A multilayer filter 10 as a preferred embodiment has a structure in which a varistor part 20 and an inductor part are stacked. The varistor part 30 consists of a stack of varistor layers 31, 32 with internal electrodes 31a, 32a, and the varistor layers contain ZnO as a principal component, and contain at least one element selected from the group consisting of Pr and Bi, Co, and Al as additives. The inductor part 20 consists of a stack of inductor layers 21-24 with conductor patterns 21a-24a, and the inductor layers contain ZnO as a principal component and substantially contain neither Co nor Al.

摘要翻译： 本发明的目的是提供一种构造成不可能在变阻器部分和电感器部分之间发生剥离的多层滤波器。 作为优选实施例的多层滤波器10具有其中堆叠有变阻器部件20和电感器部件的结构。 变阻器部分30由一组具有内部电极31a，32a的可变电阻层31,32组成，并且变阻器层含有ZnO作为主要成分，并且含有选自Pr和Bi，Co中的至少一种元素， 和Al作为添加剂。 电感器部分20由具有导体图案21a-24a的电感器层21-24的叠层组成，并且电感器层包含ZnO作为主要成分并且基本上不含有Co或Al。

公开(公告)号：US07502213B2

公开(公告)日：2009-03-10

申请号：US11449624

申请日：2006-06-09

申请人： Dai Matsuoka ,  Yuji Terada ,  Katsunari Moriai

发明人： Dai Matsuoka ,  Yuji Terada ,  Katsunari Moriai

IPC分类号： H02H1/00

CPC分类号： H01G4/40 ,  H01F2017/0026 ,  H01G2/14 ,  H02H9/04 ,  H03H7/0107 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1725 ,  H03H7/1758 ,  H03H7/38 ,  H03H2001/0085

摘要： A surge absorber has a first terminal electrode, a second terminal electrode, a third terminal electrode, an inductor portion, a surge absorbing portion, and a capacitor portion. The inductor portion has a first internal conductor and a second internal conductor mutually coupled in a polarity-reversed relation. One end of the first internal conductor is connected to the first terminal electrode. One end of the second internal conductor is connected to the second terminal electrode. The other end of the first internal conductor is connected to the other end of the second internal conductor. The surge absorbing portion has a first internal electrode connected to a connection point between the first internal conductor and the second internal conductor, and a second internal electrode connected to the third terminal electrode. The capacitor portion has a capacitance component connected between the first terminal electrode and the second terminal electrode.

摘要翻译： 浪涌吸收器具有第一端子电极，第二端子电极，第三端子电极，电感器部分，浪涌吸收部分和电容器部分。 电感器部分具有以极性相反的关系相互耦合的第一内部导体和第二内部导体。 第一内部导体的一端连接到第一端子电极。 第二内部导体的一端连接到第二端子电极。 第一内部导体的另一端连接到第二内部导体的另一端。 浪涌吸收部具有与第一内部导体和第二内部导体之间的连接点连接的第一内部电极和与第三端子电极连接的第二内部电极。 电容器部分具有连接在第一端子电极和第二端子电极之间的电容部件。

公开(公告)号：US07995326B2

公开(公告)日：2011-08-09

申请号：US12470168

申请日：2009-05-21

申请人： Kaname Ueda ,  Dai Matsuoka ,  Naoki Chida ,  Izuru Soma ,  Hisayoshi Saito ,  Katsunari Moriai

发明人： Kaname Ueda ,  Dai Matsuoka ,  Naoki Chida ,  Izuru Soma ,  Hisayoshi Saito ,  Katsunari Moriai

IPC分类号： H01G4/228

CPC分类号： H01G4/005 ,  H01C1/142 ,  H01C7/10 ,  H01G4/12 ,  H01G4/228 ,  H01G4/30

摘要： A chip-type electronic component has: a ceramic element body; a plurality of first and second internal electrodes arranged in the ceramic element body so as to be opposed at least in part to each other; a first external connection conductor to which the plurality of first internal electrodes are connected; a second external connection conductor to which the plurality of second internal electrodes are connected; first and second terminal electrodes; a first internal connection conductor arranged in the ceramic element body and connecting the first external connection conductor and the first terminal electrode; and a second internal connection conductor arranged in the ceramic element body and connecting the second external connection conductor and the second terminal electrode. The number of the first internal connection conductor is set to be smaller than the number of the first internal electrodes and the number of the second internal connection conductor is set to be smaller than the number of the second internal electrodes.

摘要翻译： 芯片型电子元件具有：陶瓷元件体; 多个第一和第二内部电极，其布置在所述陶瓷元件主体中，以至少部分地彼此相对; 连接有多个第一内部电极的第一外部连接导体; 连接所述多个第二内部电极的第二外部连接导体; 第一和第二端子电极; 布置在所述陶瓷元件主体中并连接所述第一外部连接导体和所述第一端子电极的第一内部连接导体; 以及布置在陶瓷元件主体中并连接第二外部连接导体和第二端子电极的第二内部连接导体。 第一内部连接导体的数量被设定为小于第一内部电极的数量，并且第二内部连接导体的数量被设定为小于第二内部电极的数量。

公开(公告)号：US07167352B2

公开(公告)日：2007-01-23

申请号：US11137584

申请日：2005-05-26

申请人： Dai Matsuoka ,  Katsunari Moriai ,  Takehiko Abe ,  Koichi Ishii

发明人： Dai Matsuoka ,  Katsunari Moriai ,  Takehiko Abe ,  Koichi Ishii

IPC分类号： H01G4/228

CPC分类号： H01C7/18 ,  H01C7/1006

摘要： A multilayer chip varistor comprises a multilayer body and a pair of external electrodes formed on the multilayer body. The multilayer body has a varistor section and a pair of outer layer sections disposed so as to interpose said varistor section. The varistor section comprises a varistor layer developing a voltage nonlinear characteristic and a pair of internal electrodes disposed so as to interpose the varistor layer. The pair of external electrodes are connected to respective electrodes of the pair of internal electrodes. The relative dielectric constant of the outer layer sections is set lower than the relative dielectric constant of the region where the pair of internal electrodes in the varistor layer overlap each other.

摘要翻译： 多层片式压敏电阻器包括形成在多层体上的多层体和一对外部电极。 多层体具有变阻器部和设置成插入所述可变电阻部的一对外层部。 变阻器部分包括显影电压非线性特性的变阻器层和设置成插入可变电阻层的一对内部电极。 一对外部电极连接到该对内部电极的各个电极。 将外层部分的相对介电常数设定为低于可变电阻层中的一对内部电极彼此重叠的区域的相对介电常数。

公开(公告)号：US07649435B2

公开(公告)日：2010-01-19

申请号：US11390107

申请日：2006-03-28

申请人： Katsunari Moriai ,  Dai Matsuoka ,  Yo Saito

发明人： Katsunari Moriai ,  Dai Matsuoka ,  Yo Saito

IPC分类号： H01C7/10

CPC分类号： H01C7/18 ,  H01C1/148 ,  H01C7/1006 ,  H01C7/112

摘要： A multilayer chip varistor comprises a multilayer body in which a plurality of varistor portions are arranged along a predetermined direction, and a plurality of terminal electrodes. Each varistor portion has a varistor layer to exhibit nonlinear voltage-current characteristics, and a plurality of internal electrodes disposed so as to interpose the varistor layer between them. Each terminal electrode is disposed on a first outer surface parallel to the predetermined direction out of outer surfaces of the multilayer body and is electrically connected to a corresponding internal electrode out of the plurality of internal electrodes. Each of the plurality of internal electrodes includes a first electrode portion overlapping with another first electrode portion between adjacent internal electrodes out of the plurality of internal electrodes, and a second electrode portion led from the first electrode portion so as to be exposed in the first outer surface. The plurality of terminal electrodes are electrically connected via the respective second electrode portions to the corresponding internal electrodes.

摘要翻译： 多层芯片变阻器包括其中沿着预定方向布置多个变阻器部分的多层体和多个端子电极。 每个变阻器部分具有非线性电压 - 电流特性的变阻器层，以及设置成在它们之间插入可变电阻层的多个内部电极。 每个端子电极设置在与多层体的外表面平行的预定方向的第一外表面上，并且与多个内部电极中的对应的内部电极电连接。 所述多个内部电极中的每一个包括与所述多个内部电极之间的相邻内部电极之间的另一个第一电极部分重叠的第一电极部分和从所述第一电极部分引出以暴露在所述第一外部电极中的第二电极部分 表面。 多个端子电极经由各自的第二电极部分电连接到相应的内部电极。

公开(公告)号：US20090296312A1

公开(公告)日：2009-12-03

申请号：US12470168

申请日：2009-05-21

申请人： Kaname Ueda ,  Dai Matsuoka ,  Naoki Chida ,  Izuru Soma ,  Hisayoshi Saito ,  Katsunari Moriai

发明人： Kaname Ueda ,  Dai Matsuoka ,  Naoki Chida ,  Izuru Soma ,  Hisayoshi Saito ,  Katsunari Moriai

IPC分类号： H01G4/228 ,  H01C7/10 ,  H01C1/142

CPC分类号： H01G4/005 ,  H01C1/142 ,  H01C7/10 ,  H01G4/12 ,  H01G4/228 ,  H01G4/30

摘要： A chip-type electronic component has: a ceramic element body; a plurality of first and second internal electrodes arranged in the ceramic element body so as to be opposed at least in part to each other; a first external connection conductor to which the plurality of first internal electrodes are connected; a second external connection conductor to which the plurality of second internal electrodes are connected; first and second terminal electrodes; a first internal connection conductor arranged in the ceramic element body and connecting the first external connection conductor and the first terminal electrode; and a second internal connection conductor arranged in the ceramic element body and connecting the second external connection conductor and the second terminal electrode. The number of the first internal connection conductor is set to be smaller than the number of the first internal electrodes and the number of the second internal connection conductor is set to be smaller than the number of the second internal electrodes.

摘要翻译： 芯片型电子元件具有：陶瓷元件体; 多个第一和第二内部电极，其布置在所述陶瓷元件主体中，以至少部分地彼此相对; 连接有多个第一内部电极的第一外部连接导体; 连接所述多个第二内部电极的第二外部连接导体; 第一和第二端子电极; 布置在所述陶瓷元件主体中并连接所述第一外部连接导体和所述第一端子电极的第一内部连接导体; 以及布置在陶瓷元件主体中并连接第二外部连接导体和第二端子电极的第二内部连接导体。 第一内部连接导体的数量被设定为小于第一内部电极的数量，并且第二内部连接导体的数量被设定为小于第二内部电极的数量。

公开(公告)号：US20070002513A1

公开(公告)日：2007-01-04

申请号：US11449624

申请日：2006-06-09

申请人： Dai Matsuoka ,  Yuji Terada ,  Katsunari Moriai

发明人： Dai Matsuoka ,  Yuji Terada ,  Katsunari Moriai

IPC分类号： H02H9/06

CPC分类号： H01G4/40 ,  H01F2017/0026 ,  H01G2/14 ,  H02H9/04 ,  H03H7/0107 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1725 ,  H03H7/1758 ,  H03H7/38 ,  H03H2001/0085

摘要： A surge absorber has a first terminal electrode, a second terminal electrode, a third terminal electrode, an inductor portion, a surge absorbing portion, and a capacitor portion. The inductor portion has a first internal conductor and a second internal conductor mutually coupled in a polarity-reversed relation. One end of the first internal conductor is connected to the first terminal electrode. One end of the second internal conductor is connected to the second terminal electrode. The other end of the first internal conductor is connected to the other end of the second internal conductor. The surge absorbing portion has a first internal electrode connected to a connection point between the first internal conductor and the second internal conductor, and a second internal electrode connected to the third terminal electrode. The capacitor portion has a capacitance component connected between the first terminal electrode and the second terminal electrode.

摘要翻译： 浪涌吸收器具有第一端子电极，第二端子电极，第三端子电极，电感器部分，浪涌吸收部分和电容器部分。 电感器部分具有以极性相反的关系相互耦合的第一内部导体和第二内部导体。 第一内部导体的一端连接到第一端子电极。 第二内部导体的一端连接到第二端子电极。 第一内部导体的另一端连接到第二内部导体的另一端。 浪涌吸收部具有与第一内部导体和第二内部导体之间的连接点连接的第一内部电极和与第三端子电极连接的第二内部电极。 电容器部分具有连接在第一端子电极和第二端子电极之间的电容部件。

公开(公告)号：US20060250211A1

公开(公告)日：2006-11-09

申请号：US11390107

申请日：2006-03-28

申请人： Katsunari Moriai ,  Dai Matsuoka ,  Yo Saito

发明人： Katsunari Moriai ,  Dai Matsuoka ,  Yo Saito

IPC分类号： H01C7/10

CPC分类号： H01C7/18 ,  H01C1/148 ,  H01C7/1006 ,  H01C7/112

摘要： A multilayer chip varistor comprises a multilayer body in which a plurality of varistor portions are arranged along a predetermined direction, and a plurality of terminal electrodes. Each varistor portion has a varistor layer to exhibit nonlinear voltage-current characteristics, and a plurality of internal electrodes disposed so as to interpose the varistor layer between them. Each terminal electrode is disposed on a first outer surface parallel to the predetermined direction out of outer surfaces of the multilayer body and is electrically connected to a corresponding internal electrode out of the plurality of internal electrodes. Each of the plurality of internal electrodes includes a first electrode portion overlapping with another first electrode portion between adjacent internal electrodes out of the plurality of internal electrodes, and a second electrode portion led from the first electrode portion so as to be exposed in the first outer surface. The plurality of terminal electrodes are electrically connected via the respective second electrode portions to the corresponding internal electrodes.

摘要翻译： 多层芯片变阻器包括其中沿着预定方向布置多个变阻器部分的多层体和多个端子电极。 每个变阻器部分具有非线性电压 - 电流特性的变阻器层，以及设置成在它们之间插入可变电阻层的多个内部电极。 每个端子电极设置在与多层体的外表面平行的预定方向的第一外表面上，并且与多个内部电极中的对应的内部电极电连接。 所述多个内部电极中的每一个包括与所述多个内部电极之间的相邻内部电极之间的另一个第一电极部分重叠的第一电极部分和从所述第一电极部分引出以暴露在所述第一外部电极中的第二电极部分 表面。 多个端子电极经由各自的第二电极部分电连接到相应的内部电极。

公开(公告)号：US20050276001A1

公开(公告)日：2005-12-15

申请号：US11137584

申请日：2005-05-26

申请人： Dai Matsuoka ,  Katsunari Moriai ,  Takehiko Abe ,  Koichi Ishii

发明人： Dai Matsuoka ,  Katsunari Moriai ,  Takehiko Abe ,  Koichi Ishii

IPC分类号： H01C7/10 ,  H01C7/18 ,  H01G4/228

CPC分类号： H01C7/18 ,  H01C7/1006

摘要： A multilayer chip varistor comprises a multilayer body and a pair of external electrodes formed on the multilayer body. The multilayer body has a varistor section and a pair of outer layer sections disposed so as to interpose said varistor section. The varistor section comprises a varistor layer developing a voltage nonlinear characteristic and a pair of internal electrodes disposed so as to interpose the varistor layer. The pair of external electrodes are connected to respective electrodes of the pair of internal electrodes. The relative dielectric constant of the outer layer sections is set lower than the relative dielectric constant of the region where the pair of internal electrodes in the varistor layer overlap each other.

摘要翻译： 多层片式压敏电阻器包括形成在多层体上的多层体和一对外部电极。 多层体具有变阻器部和设置成插入所述可变电阻部的一对外层部。 变阻器部分包括显影电压非线性特性的变阻器层和设置成插入可变电阻层的一对内部电极。 一对外部电极连接到该对内部电极的各个电极。 将外层部分的相对介电常数设定为低于可变电阻层中的一对内部电极彼此重叠的区域的相对介电常数。