公开(公告)号：US20100213534A1

公开(公告)日：2010-08-26

申请号：US12709154

申请日：2010-02-19

申请人： Katsuyuki SEKINE ,  Katsuaki Natori ,  Tetsuya Kai ,  Yoshio Ozawa

发明人： Katsuyuki SEKINE ,  Katsuaki Natori ,  Tetsuya Kai ,  Yoshio Ozawa

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L29/40114 ,  H01L29/42336

摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors, each of the memory cell transistors has a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and element isolation insulating films respectively. The floating gate electrode on the tunnel insulating film is provided with a first floating gate electrode and a second floating gate electrode formed sequentially from the bottom, the second floating gate electrode being narrower in a channel-width direction than the first one. Levels of upper surfaces of the element isolation insulating films and the first floating gate electrode are the same. The inter-electrode insulating film continuously covers the upper and side surfaces of the floating gate electrode and the upper surfaces of the element isolation insulating films, and is higher in a nitrogen concentration in a boundary portion to the floating gate electrode than in boundary portions to the element isolation insulating films.

摘要翻译： 在设置有存储单元晶体管的非易失性半导体存储器件中，每个存储单元晶体管分别具有隧道绝缘膜，浮栅电极，电极间绝缘膜和元件隔离绝缘膜。 隧道绝缘膜上的浮栅电极设置有从底部顺序形成的第一浮栅电极和第二浮栅电极，第二浮栅电极在沟道宽度方向比第一浮栅电极和第一浮栅电极窄。 元件隔离绝缘膜和第一浮栅电极的上表面的电平相同。 电极间绝缘膜连续地覆盖浮置栅电极的上表面和元件隔离绝缘膜的上表面，并且在与栅极电极的边界部分的氮浓度相比高于边界部分 元件隔离绝缘膜。

公开(公告)号：US08829593B2

公开(公告)日：2014-09-09

申请号：US12726952

申请日：2010-03-18

申请人： Katsuyuki Sekine ,  Kensuke Takano ,  Masaaki Higuchi ,  Tetsuya Kai ,  Yoshio Ozawa

发明人： Katsuyuki Sekine ,  Kensuke Takano ,  Masaaki Higuchi ,  Tetsuya Kai ,  Yoshio Ozawa

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L29/423 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

摘要： A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.

摘要翻译： 第一选择晶体管形成在半导体衬底上。 存储单元晶体管堆叠在第一选择晶体管上并串联连接。 在存储单元晶体管上形成第二选择晶体管。 存储单元晶体管包括从第一选择晶体管朝向第二选择晶体管的直径增加的锥形半导体柱，形成在半导体柱的侧表面上的隧道电介质膜，形成在半导体柱的侧表面上的电荷存储层 隧道电介质膜，并且其从第一选择晶体管侧朝向第二选择晶体管侧的电荷陷阱密度增加，形成在电荷存储层的侧表面上的块状电介质膜和形成在电荷存储层的侧表面上的导体膜 该块介质膜并用作栅电极。

公开(公告)号：US20110175157A1

公开(公告)日：2011-07-21

申请号：US13008469

申请日：2011-01-18

申请人： Katsuyuki SEKINE ,  Tetsuya Kai ,  Yoshio Ozawa

发明人： Katsuyuki SEKINE ,  Tetsuya Kai ,  Yoshio Ozawa

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer; first and second insulating layers; a functional layer; first and second gate electrodes. The first insulating layer opposes the semiconductor layer. The second insulating layer is provided between the semiconductor layer and the first insulating layer. The functional layer is provided between the first and second insulating layers. The second gate electrode is separated from the first gate electrode. The first insulating layer is disposed between the first gate electrode and the semiconductor layer and between the second gate electrode and the semiconductor layer. The charge storabilities in first and second regions of the functional layer are different from that of a third region of the functional layer. The first and second regions oppose the first and second gate electrodes, respectively. The third region is between the first and the second regions.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括半导体层; 第一和第二绝缘层; 功能层; 第一和第二栅电极。 第一绝缘层与半导体层相对。 第二绝缘层设置在半导体层和第一绝缘层之间。 功能层设置在第一和第二绝缘层之间。 第二栅电极与第一栅电极分离。 第一绝缘层设置在第一栅电极和半导体层之间以及第二栅电极和半导体层之间。 功能层的第一和第二区域中的电荷存储能力与功能层的第三区域的电荷存储能力不同。 第一和第二区域分别与第一和第二栅电极相对。 第三区域在第一和第二区域之间。

公开(公告)号：US07521263B2

公开(公告)日：2009-04-21

申请号：US11270536

申请日：2005-11-10

申请人： Ichiro Mizushima ,  Masayuki Tanaka ,  Katsuaki Natori ,  Yoshio Ozawa ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Tetsuya Kai

发明人： Ichiro Mizushima ,  Masayuki Tanaka ,  Katsuaki Natori ,  Yoshio Ozawa ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Tetsuya Kai

IPC分类号： H01L21/00

CPC分类号： H01L21/02236 ,  H01L21/022 ,  H01L21/28273 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/7881

摘要： A method of forming an insulating film includes forming a base film comprising a material whose surface is oxidized by being exposed to an oxidant. A source gas containing a metal material and a first oxidant having a first oxidation force are alternately supplied to form a first insulating film on the base film. A source gas containing a metal material and a second oxidant having a second oxidation force stronger than the first oxidation force are alternately supplied to form a second insulating film on the first insulating film.

摘要翻译： 形成绝缘膜的方法包括形成包括通过暴露于氧化剂而使其表面被氧化的材料的基膜。 交替地供给含有金属材料的源气体和具有第一氧化力的第一氧化剂，以在基膜上形成第一绝缘膜。 交替地供给含有金属材料的源气体和具有比第一氧化力更强的第二氧化力的第二氧化剂，以在第一绝缘膜上形成第二绝缘膜。

公开(公告)号：US20070020957A1

公开(公告)日：2007-01-25

申请号：US11270536

申请日：2005-11-10

申请人： Ichiro Mizushima ,  Masayuki Tanaka ,  Katsuaki Natori ,  Yoshio Ozawa ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Tetsuya Kai

发明人： Ichiro Mizushima ,  Masayuki Tanaka ,  Katsuaki Natori ,  Yoshio Ozawa ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Tetsuya Kai

IPC分类号： B05D3/08 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02236 ,  H01L21/022 ,  H01L21/28273 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/7881

摘要： A method of forming an insulating film includes forming a base film comprising a material whose surface is oxidized by being exposed to an oxidant. A source gas containing a metal material and a first oxidant having a first oxidation force are alternately supplied to form a first insulating film on the base film. A source gas containing a metal material and a second oxidant having a second oxidation force stronger than the first oxidation force are alternately supplied to form a second insulating film on the first insulating film.

摘要翻译： 形成绝缘膜的方法包括形成包括通过暴露于氧化剂而使其表面被氧化的材料的基膜。 交替地供给含有金属材料的源气体和具有第一氧化力的第一氧化剂，以在基膜上形成第一绝缘膜。 交替地供给含有金属材料的源气体和具有比第一氧化力更强的第二氧化力的第二氧化剂，以在第一绝缘膜上形成第二绝缘膜。

公开(公告)号：US20120034754A1

公开(公告)日：2012-02-09

申请号：US13272457

申请日：2011-10-13

申请人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

发明人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

摘要翻译： 半导体器件制造方法在半导体衬底中具有形成元件隔离沟槽，在元件隔离沟槽的内部形成硅化合物膜，以便嵌入元件隔离沟槽，在第一温度下进行第一氧化处理以使表面 所述硅化合物膜能够通过氧化剂和杂质而不允许含有硅原子的挥发性物质通过的挥发性物质排放防止层，并且在比所述第一温度高的第二温度下进行第二氧化处理 温度以在元件隔离槽内形成被覆氧化硅膜。

公开(公告)号：US08080463B2

公开(公告)日：2011-12-20

申请号：US12691483

申请日：2010-01-21

申请人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

发明人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

摘要翻译： 半导体器件制造方法在半导体衬底中具有形成元件隔离沟槽，在元件隔离沟槽的内部形成硅化合物膜，以便嵌入元件隔离沟槽，在第一温度下进行第一氧化处理以使表面 所述硅化合物膜能够通过氧化剂和杂质而不允许含有硅原子的挥发性物质通过的挥发性物质排放防止层，并且在比所述第一温度高的第二温度下进行第二氧化处理 温度以在元件隔离槽内形成被覆氧化硅膜。

公开(公告)号：US20100190317A1

公开(公告)日：2010-07-29

申请号：US12691483

申请日：2010-01-21

申请人： Kazuaki IWASAWA ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

发明人： Kazuaki IWASAWA ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

摘要翻译： 半导体器件制造方法在半导体衬底中具有形成元件隔离沟槽，在元件隔离沟槽的内部形成硅化合物膜，以便嵌入元件隔离沟槽，在第一温度下进行第一氧化处理以使表面 所述硅化合物膜能够通过氧化剂和杂质而不允许含有硅原子的挥发性物质通过的挥发性物质排放防止层，并且在比所述第一温度高的第二温度下进行第二氧化处理 温度以在元件隔离槽内形成被覆氧化硅膜。

公开(公告)号：US08803221B2

公开(公告)日：2014-08-12

申请号：US13231776

申请日：2011-09-13

申请人： Tetsuya Kai ,  Yoshio Ozawa

发明人： Tetsuya Kai ,  Yoshio Ozawa

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L21/76224 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/792

摘要： In one embodiment, a nonvolatile semiconductor memory device includes a substrate; a tunnel insulating film on the substrate; a charge storage layer on the tunnel insulating film; a block insulating film on the charge storage layer; a first element isolation insulating film in an element isolation trench in the substrate, having a bottom surface lower than an interface between the substrate and the tunnel insulating film, and having a top surface lower than an interface between the charge storage layer and the block insulating film; a second element isolation insulating film on the first element isolation insulating film, protruding to a top surface of the block insulating film, in contact with a side surface of the block insulating film, and having a higher Si concentration than the block insulating film; and a control gate electrode on the block insulating film and on the second element isolation insulating film.

摘要翻译： 在一个实施例中，非易失性半导体存储器件包括衬底; 衬底上的隧道绝缘膜; 隧道绝缘膜上的电荷存储层; 电荷存储层上的块绝缘膜; 在衬底中的元件隔离沟槽中的第一元件隔离绝缘膜，其底表面低于衬底和隧道绝缘膜之间的界面，并且具有低于电荷存储层和块绝缘体之间的界面的顶表面 电影; 第一元件隔离绝缘膜上的第二元件隔离绝缘膜突出到块绝缘膜的顶表面，与块绝缘膜的侧表面接触，并且具有比嵌段绝缘膜更高的Si浓度; 以及在所述块绝缘膜上和所述第二元件隔离绝缘膜上的控制栅电极。

公开(公告)号：US20100157680A1

公开(公告)日：2010-06-24

申请号：US12638836

申请日：2009-12-15

申请人： Masaaki Higuchi ,  Hiroshi Matsuba ,  Yoshio Ozawa ,  Tetsuya Kai

发明人： Masaaki Higuchi ,  Hiroshi Matsuba ,  Yoshio Ozawa ,  Tetsuya Kai

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L21/28 ,  G11C11/34

CPC分类号： H01L21/28282

摘要： A semiconductor device includes a semiconductor region, a tunnel insulating film formed on the semiconductor region, a charge-storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge-storage insulating film, and a control gate electrode formed on the block insulating film, wherein the tunnel insulating film comprises a first region which is formed on a surface of the semiconductor region and contains silicon and oxygen, a second region which contains silicon and nitrogen, a third region which is formed on a back surface of the charge-storage insulating film and contains silicon and oxygen, and an insulating region which is formed at least between the first region and the second region or between the second region and the third region, and contains silicon and nitrogen and oxygen and the second region is formed between the first region and the third region.

摘要翻译： 半导体器件包括半导体区域，形成在半导体区域上的隧道绝缘膜，形成在隧道绝缘膜上的电荷存储绝缘膜，形成在电荷存储绝缘膜上的块绝缘膜和形成的控制栅电极 在所述块绝缘膜上，其中所述隧道绝缘膜包括形成在所述半导体区域的表面上并且包含硅和氧的第一区域，包含硅和氮的第二区域，形成在所述第二区域的背面 的电荷存储绝缘膜并且包含硅和氧，以及至少形成在第一区域和第二区域之间或者在第二区域和第三区域之间形成的绝缘区域，并且包含硅和氮和氧，并且第二 区域形成在第一区域和第三区域之间。