公开(公告)号：US08053257B2

公开(公告)日：2011-11-08

申请号：US12061104

申请日：2008-04-02

申请人： Kaushik Chanda ,  Hazara S. Rathore ,  Paul S. McLaughlin ,  Robert D. Edwards ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Chih-Chao Yang ,  Conrad A. Barile

发明人： Kaushik Chanda ,  Hazara S. Rathore ,  Paul S. McLaughlin ,  Robert D. Edwards ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Chih-Chao Yang ,  Conrad A. Barile

IPC分类号： H01L21/00

CPC分类号： G06F17/5009 ,  G01R31/287 ,  G06F2217/10 ,  G06F2217/70 ,  G06F2217/78

摘要： The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for a layer within chips comprising a semiconductor wafer lot. If only one mode is calculated, that is the best calculated mode. If multiple modes can be calculated, a best mode that most accurately represents dielectric breakdown for the semiconductor wafer lot is determined. Premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation from the best calculated mode.

摘要翻译： 本发明预测半导体中的过早的介质击穿。 对包括半导体晶片批次的芯片内的层计算至少一个介电击穿模式。 如果只计算一种模式，那就是最好的计算模式。 如果可以计算多种模式，则确定最准确地代表半导体晶片批次的绝缘击穿的最佳模式。 过早的介质击穿将与任何具有小于最佳计算模式的预定标准偏差的击穿电压的半导体相关联。

公开(公告)号：US20080174334A1

公开(公告)日：2008-07-24

申请号：US12061104

申请日：2008-04-02

申请人： Kaushik Chanda ,  Hazara S. Rathore ,  Paul S. McLaughlin ,  Robert D. Edwards ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Chih-Chao Yang ,  Conrad A. Barile

发明人： Kaushik Chanda ,  Hazara S. Rathore ,  Paul S. McLaughlin ,  Robert D. Edwards ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Chih-Chao Yang ,  Conrad A. Barile

IPC分类号： G01R31/26 ,  G06F17/50

CPC分类号： G06F17/5009 ,  G01R31/287 ,  G06F2217/10 ,  G06F2217/70 ,  G06F2217/78

摘要： The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.

摘要翻译： 本发明预测半导体中的过早的介质击穿。 对于半导体晶片计算至少一个介电击穿模式。 如果计算一种模式，则过早的介电击穿将与在所述计算模式中具有小于多个击穿电压的预定标准偏差的击穿电压的任何半导体相关联。 如果计算多个模式，则确定最准确地代表半导体晶片的电介质击穿的模式，并且过早的电介质击穿将与任何具有小于计算模式的预定标准的击穿电压的半导体相关联，其最准确地表示用于 半导体晶片。

公开(公告)号：US07692439B2

公开(公告)日：2010-04-06

申请号：US12154304

申请日：2008-05-22

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/02 ,  H01L23/58 ,  G01N25/20

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

摘要翻译： 提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平 延伸平面 该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。 下导电或半导体元件可以与下通孔的底端接触。 上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。 上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。 该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

公开(公告)号：US20080231312A1

公开(公告)日：2008-09-25

申请号：US12154304

申请日：2008-05-22

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

摘要翻译： 提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平 延伸平面 该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。 下导电或半导体元件可以与下通孔的底端接触。 上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。 上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。 该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

公开(公告)号：US07397260B2

公开(公告)日：2008-07-08

申请号：US11163948

申请日：2005-11-04

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/02 ,  H01L23/58 ,  G01N25/20

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US07639032B2

公开(公告)日：2009-12-29

申请号：US12004011

申请日：2007-12-19

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/02 ,  H01L23/58 ,  G01N25/20

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US07585764B2

公开(公告)日：2009-09-08

申请号：US11161599

申请日：2005-08-09

申请人： Kaushik Chanda ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Jason P. Gill ,  Baozhen Li ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Jason P. Gill ,  Baozhen Li ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76865 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76886

摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.

摘要翻译： 制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。 该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。 该方法产生防止开路的结构。

公开(公告)号：US07830019B2

公开(公告)日：2010-11-09

申请号：US12431289

申请日：2009-04-28

申请人： Kaushik Chanda ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Jason P. Gill ,  Baozhen Li ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Jason P. Gill ,  Baozhen Li ,  Chih-Chao Yang

IPC分类号： H01L23/04

CPC分类号： H01L21/76865 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76886

摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.

摘要翻译： 制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。 该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。 该方法产生防止开路的结构。

公开(公告)号：US20090200673A1

公开(公告)日：2009-08-13

申请号：US12431289

申请日：2009-04-28

申请人： Kaushik Chanda ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Jason P. Gill ,  Baozhen Li ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Jason P. Gill ,  Baozhen Li ,  Chih-Chao Yang

IPC分类号： H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76865 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76886

摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.

摘要翻译： 制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。 该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。 该方法产生防止开路的结构。

公开(公告)号：US07598616B2

公开(公告)日：2009-10-06

申请号：US12140352

申请日：2008-06-17

申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

IPC分类号： H01L29/06 ,  H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure. The structure includes: a core electrical conductor having a top surface, an opposite bottom surface and sides between the top and bottom surfaces; an electrically conductive liner in direct physical contact with and covering the bottom surface and the sides of the core electrical conductor, embedded portions of the electrically conductive liner in direct physical contact with and extending over the core electrical conductor in regions of the core electrical conductor adjacent to both the top surface and the sides of the core electrical conductor; and an electrically conductive cap in direct physical contact with the top surface of the core electrical conductor that is exposed between the embedded portions of the electrically conductive liner.

摘要翻译： 一个结构。 该结构包括：具有顶表面，相对的底表面和顶表面和底表面之间的侧面的芯电导体; 与芯电导体的底表面和侧面直接物理接触并覆盖芯电导体的底表面和侧面的导电衬垫，导电衬垫的嵌入部分与芯电导体相邻的芯电导体的区域中直接物理接触并延伸 到芯电导体的顶表面和侧面; 以及与导电衬里的嵌入部分之间暴露的芯电导体的顶表面直接物理接触的导电帽。