利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

139 条记录 (耗时 0.028 秒)

    Acoustic data output device having single addressable memory
    1.
    发明授权
    Acoustic data output device having single addressable memory 失效
    具有单个可寻址存储器的声学数据输出装置

    公开(公告)号：US5303629A

    公开(公告)日：1994-04-19

    申请号：US661729

    申请日：1991-02-26

    申请人： Kazuhiko Yokota ,  Kazuhisa Mito ,  Yoshio Kimura

    发明人： Kazuhiko Yokota ,  Kazuhisa Mito ,  Yoshio Kimura

    IPC分类号： G10K15/04 ,  G10H1/26 ,  G10K15/02 ,  G10H7/00 ,  G10H1/18

    CPC分类号： G10K15/02 ,  G10H1/26 ,  G10H2230/351

    摘要： An acoustic data output device comprises an addressable memory for storing acoustic data. A plurality of clock signals are coupled to count separate address counters of a number corresponding to the number of clock signals. A signal selector is responsive to the clock signals for providing an address counter selection signal, whereby at any given time the selection signal corresponds to a separate one of the address counters. An addressing device is responsive to the address counter selection signal for selectively addressing the addressable memory with the count of the corresponding address counter. A separate data latch corresponds to each address counter and the data latches are coupled to receive the output of said addressable memory. The outputs of the data latches are synchronized with the clock signal corresponding thereto.

    摘要翻译： 声学数据输出装置包括用于存储声学数据的可寻址存储器。 多个时钟信号被耦合以对与时钟信号的数量相对应的数字的单独的地址计数器进行计数。 信号选择器响应于时钟信号以提供地址计数器选择信号，由此在任何给定时间，选择信号对应于地址计数器的单独一个。 寻址设备响应于地址计数器选择信号，用于对应地址计数器的计数来选择性地寻址可寻址存储器。 单独的数据锁存器对应于每个地址计数器，并且数据锁存器被耦合以接收所述可寻址存储器的输出。 数据锁存器的输出与对应的数据锁存器的时钟信号同步。

    COATING AND DEVELOPING APPARATUS
    2.
    发明申请
    COATING AND DEVELOPING APPARATUS 审中-公开

    公开(公告)号：US20100326353A1

    公开(公告)日：2010-12-30

    申请号：US12855524

    申请日：2010-08-12

    申请人： Masami AKIMOTO ,  Shinichi Hayashi ,  Yasushi Hayashida ,  Nobuaki Matsuoka ,  Yoshio Kimura ,  Issei Ueda ,  Hikaru Ito

    发明人： Masami AKIMOTO ,  Shinichi Hayashi ,  Yasushi Hayashida ,  Nobuaki Matsuoka ,  Yoshio Kimura ,  Issei Ueda ,  Hikaru Ito

    IPC分类号： B05C9/12

    CPC分类号： H01L21/67184 ,  H01L21/67173 ,  H01L21/67178 ,  H01L21/67207 ,  H01L21/67745

    摘要： Provided is a coating and developing apparatus composed of an assembly of plural unit blocks. A first unit-block stack and a second unit-block stack are arranged at different positions with respect to front-and-rear direction. Unit blocks for development, each of which comprises plural processing units including a developing unit that performs developing process after exposure and a transfer device that transfers a substrate among the processing units, are arranged at the lowermost level. Unit blocks for application, or coating, each of which comprises plural processing units including a coating unit that performs application process before exposure and a transfer device that transfers a substrate among the processing units, are arranged above the unit blocks for development. Unit blocks for application are arranged in both the first and second unit-block stacks. Unit blocks for application which a wafer goes through are determined depending on the layering positional relationship between an antireflective film and a resist film. An exposed wafer goes only through the unit block for development without going through any one of the unit blocks for application.

    Heating apparatus, and coating and developing apparatus
    4.
    发明授权
    Heating apparatus, and coating and developing apparatus 有权
    加热装置和涂装显影装置

    公开(公告)号：US07797855B2

    公开(公告)日：2010-09-21

    申请号：US11505810

    申请日：2006-08-18

    申请人： Tetsuo Fukuoka ,  Masami Akimoto ,  Takahiro Kitano ,  Yoshio Kimura ,  Shinichi Hayashi ,  Hikaru Ito

    发明人： Tetsuo Fukuoka ,  Masami Akimoto ,  Takahiro Kitano ,  Yoshio Kimura ,  Shinichi Hayashi ,  Hikaru Ito

    IPC分类号： F26B21/06

    CPC分类号： C30B33/02 ,  C30B35/00 ,  H01L21/67098 ,  H01L21/67748

    摘要： A heating apparatus 2 comprises a housing 20; a flat heating chamber 4 which is provided in the housing 2 and adapted to heat a wafer W used as a substrate, with one side of the heating chamber 4 opening for carrying in and carrying out the wafer; and a heating plates 44, 45 provided in the heating chamber 4 such that the wafer W can be heated from both above and below. A cooling plate 3 is provided in the housing 20 located in the vicinity of the opening of the heating chamber 4, for cooling the wafer W after being heated by the heating plates 44, 45. Additionally, a carrying means is provided in the housing 20 for carrying the wafer W between an upper position of the cooling plate 3 and the interior of the heating chamber 4 such that a heat treatment for the wafer W can be performed with the wafer W being held in the heating chamber 4.

    摘要翻译： 加热装置2包括壳体20; 平面加热室4，其设置在壳体2中并且适于加热用作基板的晶片W，加热室4的一侧开口用于承载和执行晶片; 以及设置在加热室4中的加热板44,45，使得晶片W能够从上下两者加热。 冷却板3设置在位于加热室4的开口附近的壳体20中，用于在被加热板44,45加热之后冷却晶片W.此外，在壳体20中设置有承载装置 用于在冷却板3的上部位置和加热室4的内部之间承载晶片W，使得可以在将晶片W保持在加热室4中的情况下进行晶片W的热处理。

    Coating and developing apparatus
    5.
    发明授权
    Coating and developing apparatus 有权
    涂装显影装置

    公开(公告)号：US07793609B2

    公开(公告)日：2010-09-14

    申请号：US11342616

    申请日：2006-01-31

    申请人： Masami Akimoto ,  Shinichi Hayashi ,  Yasushi Hayashida ,  Nobuaki Matsuoka ,  Yoshio Kimura ,  Issei Ueda ,  Hikaru Ito

    发明人： Masami Akimoto ,  Shinichi Hayashi ,  Yasushi Hayashida ,  Nobuaki Matsuoka ,  Yoshio Kimura ,  Issei Ueda ,  Hikaru Ito

    IPC分类号： B05C5/02

    CPC分类号： H01L21/67184 ,  H01L21/67173 ,  H01L21/67178 ,  H01L21/67207 ,  H01L21/67745

    摘要： Provided is a coating and developing apparatus composed of an assembly of plural unit blocks. A first unit-block stack and a second unit-block stack are arranged at different positions with respect to front-and-rear direction. Unit blocks for development, each of which comprises plural processing units including a developing unit that performs developing process after exposure and a transfer device that transfers a substrate among the processing units, are arranged at the lowermost level. Unit blocks for application, or coating, each of which comprises plural processing units including a coating unit that performs application process before exposure and a transfer device that transfers a substrate among the processing units, are arranged above the unit blocks for development. Unit blocks for application are arranged in both the first and second unit-block stacks. Unit blocks for application which a wafer goes through are determined depending on the layering positional relationship between an antireflective film and a resist film. An exposed wafer goes only through the unit block for development without going through any one of the unit blocks for application.

    摘要翻译： 提供一种由多个单元块组成的涂层显影装置。 第一单位块堆叠和第二单位块堆叠被布置在相对于前后方向的不同位置。 用于显影的单元块，每个包括多个处理单元，包括执行曝光之后的显影处理的显影单元和在处理单元之间传送基板的转印装置布置在最下层。 用于应用或涂布的单元块包括多个处理单元，其包括在曝光之前进行施加处理的涂布单元和在处理单元之间传送基板的转印装置，布置在用于显影的单位块上方。 用于应用的单元块被布置在第一和第二单元块堆叠中。 根据防反射膜和抗蚀剂膜之间的层叠位置关系确定晶片通过的应用单元块。 暴露的晶片仅通过单元块进行开发，而不经过用于应用的单元块中的任何一个。

    RESIST PATTERN FORMING METHOD
    7.
    发明申请
    RESIST PATTERN FORMING METHOD 有权
    电阻图案形成方法

    公开(公告)号：US20100047702A1

    公开(公告)日：2010-02-25

    申请号：US12610907

    申请日：2009-11-02

    申请人： Kunie OGATA ,  Koki Nishimuko ,  Hiroshi Tomita ,  Yoshio Kimura ,  Ryouichi Uemura ,  Michio Tanaka

    发明人： Kunie OGATA ,  Koki Nishimuko ,  Hiroshi Tomita ,  Yoshio Kimura ,  Ryouichi Uemura ,  Michio Tanaka

    IPC分类号： G03F7/20 ,  G03B27/32

    CPC分类号： H01L21/67253 ,  G03F7/162 ,  G03F7/3021 ,  H01L21/6715

    摘要： A resist pattern forming method using a coating and developing apparatus and an aligner being connected thereto which are controlled to form a resist film on a surface of a substrate with a base film and a base pattern formed thereon, followed by inspecting at least one of a plurality of measurement items selected from: reflection ratio and film thickness of the base film and the resist film, line width after a development, an accuracy that the base pattern matches with a resist pattern, a defect on the surface after the development, etc. A parameter subject to amendment is selected based on corresponding data of each measurement item, such as the film thickness of the resist and the line width after the development, and amendment of the parameter is performed. This results in a reduced workload of an operator, and the appropriate amendment can be performed.

    摘要翻译： 使用涂覆和显影装置和对准器连接的抗蚀剂图案形成方法被控制以在其上形成有基膜和基底图案的基板的表面上形成抗蚀剂膜，然后检查至少一个 选自以下的多个测量项目：基膜和抗蚀剂膜的反射率和膜厚度，显影后的线宽度，基底图案与抗蚀剂图案匹配的精度，显影后的表面上的缺陷等。 基于每个测量项目的对应数据（例如抗蚀剂的膜厚度和显影后的线宽度）来选择修改参数，并且修改参数。 这导致操作者的工作量减少，并且可以执行适当的修改。

    Coating and developing system and coating and developing method
    8.
    发明授权
    Coating and developing system and coating and developing method 有权
    涂层开发系统及涂层开发方法

    公开(公告)号：US07281869B2

    公开(公告)日：2007-10-16

    申请号：US11335635

    申请日：2006-01-20

    申请人： Masami Akimoto ,  Shinichi Hayashi ,  Yasushi Hayashida ,  Nobuaki Matsuoka ,  Yoshio Kimura ,  Issei Ueda ,  Hikaru Ito

    发明人： Masami Akimoto ,  Shinichi Hayashi ,  Yasushi Hayashida ,  Nobuaki Matsuoka ,  Yoshio Kimura ,  Issei Ueda ,  Hikaru Ito

    IPC分类号： G03B5/00

    CPC分类号： H01L21/67184 ,  H01L21/00 ,  H01L21/6715 ,  H01L21/67178 ,  H01L21/6719

    摘要： A coating and developing system includes a resist film forming unit block and antireflection film forming unit blocks stacked up in layers to form a resist film and an antireflection film underlying the resist film and an antireflection film overlying the resist film in a small space. The coating and developing system can cope with a case where antireflection films are formed and a case where any antireflection film is not formed. Film forming unit blocks, namely, a TCT layer, a COT layer and a BCT layer, and developing unit blocks, namely, DEV layers, are stacked up in layers in a processing block. The TCT layer, the COT layer and the BCT layer are used selectively in the case where antireflection films are formed and where no antireflection film is formed. The coating and developing system is controlled by a simple carrying program.

    摘要翻译： 涂覆显影系统包括：抗蚀剂膜形成单元块和层叠的抗反射膜形成单元块，以形成抗蚀剂膜和抗反射膜下面的抗反射膜以及在小空间中覆盖抗蚀剂膜的抗反射膜。 涂覆和显影系统可以应对形成防反射膜的情况以及没有形成任何抗反射膜的情况。 成膜单位块，即TCT层，COT层和BCT层，以及显影单元块，即DEV层，在处理块中层叠。 在形成防反射膜并且不形成抗反射膜的情况下，TCT层，COT层和BCT层被选择性地使用。 涂层和显影系统由简单的携带程序控制。

    Coating and developing system and coating and developing method
    10.
    发明申请
    Coating and developing system and coating and developing method 有权
    涂层开发系统及涂层开发方法

    公开(公告)号：US20060162646A1

    公开(公告)日：2006-07-27

    申请号：US11117552

    申请日：2005-04-29

    申请人： Masami Akimoto ,  Shinichi Hayashi ,  Yasushi Hayashida ,  Nobuaki Matsuoka ,  Yoshio Kimura ,  Issei Ueda ,  Hikaru Ito

    发明人： Masami Akimoto ,  Shinichi Hayashi ,  Yasushi Hayashida ,  Nobuaki Matsuoka ,  Yoshio Kimura ,  Issei Ueda ,  Hikaru Ito

    IPC分类号： B05D5/06 ,  B05C11/02 ,  B05C13/02

    CPC分类号： H01L21/67184 ,  H01L21/67173 ,  H01L21/67178

    摘要： A coating and developing system includes a resist film forming unit block and antireflection film forming unit blocks stacked up in layers to form a resist film and an antireflection film underlying the resist film and an antireflection film overlying the resist film in a small space. The coating and developing system is capable of coping with either of a case where antireflection films are formed and a case where any antireflection film is not formed and needs simple software. Film forming unit blocks, namely, a TCT layer B3, a COT layer B4 and a BCT layer B5, and developing unit blocks, namely, DEV layers B1 and B2, are stacked up in layers in a processing block S2. The TCT layer B3, the COT layer B4 and the BCT layer B5 are used selectively in the case where antireflection films are formed and the case where any antireflection film is not formed. The coating and developing system is controlled by a simple carrying program and simple software.

    摘要翻译： 涂覆显影系统包括：抗蚀剂膜形成单元块和层叠的抗反射膜形成单元块，以形成抗蚀剂膜和抗反射膜下面的抗反射膜以及在小空间中覆盖抗蚀剂膜的抗反射膜。 涂层显影系统能够应对形成防反射膜的情况和没有形成任何抗反射膜的情况，并且需要简单的软件。 成膜单元块，即TCT层B 3，COT层B 4和BCT层B 5以及显影单元块，即DEV层B 1和B 2，层叠在处理块S 2。 在形成防反射膜的情况下，选择性地使用TCT层B 3，COT层B 4和BCT层B 5以及未形成任何抗反射膜的情况。 涂层和显影系统由简单的携带程序和简单的软件控制。