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1.发明授权Semiconductor memory device and control method having data protection feature 有权具有数据保护特性的半导体存储器件和控制方法公开(公告)号：US07224602B2
公开(公告)日：2007-05-29
申请号：US11126869
申请日：2005-05-11
CPC分类号： G11C16/08 , G06F12/1425 , G11C16/22 , Y02D10/13
摘要： A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.
摘要翻译： 一种半导体器件包括：第一存储单元阵列，其包括用于存储数据的存储器单元，并以扇区为基础进行管理;第二存储单元阵列，包括存储器单元，该存储单元存储基于扇区的扇区保护信息;以及控制电路，检查扇区保护信息 每当选择要编程或擦除的扇区时，存储在第二存储单元阵列中。 因此，所有扇区中的扇区保护信息在上电时不必被锁存。 不必提供与扇区数量相等的锁存电路。 因此可以大大减少电路的数量，并且可以减小芯片面积。
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公开(公告)号：US20050276125A1
公开(公告)日：2005-12-15
申请号：US11126869
申请日：2005-05-11
CPC分类号： G11C16/08 , G06F12/1425 , G11C16/22 , Y02D10/13
摘要： A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.
摘要翻译： 一种半导体器件包括：第一存储单元阵列，其包括用于存储数据的存储器单元，并以扇区为基础进行管理;第二存储单元阵列，包括存储器单元，该存储单元存储基于扇区的扇区保护信息;以及控制电路，检查扇区保护信息 每当选择要编程或擦除的扇区时，存储在第二存储单元阵列中。 因此，所有扇区中的扇区保护信息在上电时不必被锁存。 不必提供与扇区数量相等的锁存电路。 因此可以大大减少电路的数量，并且可以减小芯片面积。
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公开(公告)号：US07206241B2
公开(公告)日：2007-04-17
申请号：US11126558
申请日：2005-05-11
IPC分类号： G11C7/02
CPC分类号： G11C16/12 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3445 , G11C16/3459
摘要： The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.
摘要翻译： 本发明的半导体器件包括至少一个编程状态的虚拟单元，其近似位于参考单元阵列的边缘。 因此，当读取参考单元阵列的边缘上的单元的数据时，泄漏电流不流动。 位于参考单元阵列中心周围的存储单元具有编程状态的相邻单元，并且当从所有参考单元读出数据时，可以防止泄漏电流。 因此，能够稳定地供给基准电流。
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公开(公告)号：US20050276112A1
公开(公告)日：2005-12-15
申请号：US11126558
申请日：2005-05-11
CPC分类号： G11C16/12 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3445 , G11C16/3459
摘要： The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.
摘要翻译： 本发明的半导体器件包括至少一个编程状态的虚拟单元，其近似位于参考单元阵列的边缘。 因此，当读取参考单元阵列的边缘上的单元的数据时，泄漏电流不流动。 位于参考单元阵列中心周围的存储单元具有编程状态的相邻单元，并且当从所有参考单元读出数据时，可以防止泄漏电流。 因此，能够稳定地供给基准电流。
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公开(公告)号：US07307894B2
公开(公告)日：2007-12-11
申请号：US11127712
申请日：2005-05-12
IPC分类号： G11C7/10
摘要： The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.
摘要翻译： 半导体器件包括：存储单元阵列，其包括用于存储数据的存储单元，并以扇区为基础进行管理;存储器，其存储确定激活状态的信息;锁存电路，其根据存储在存储器中的信息来锁存激活信息 以及根据存储在锁存电路中的存储器中的信息来锁存激活信息的电路。 根据存储器的存储状态的激活信息在激活之后输入给定命令时被锁存，因此可以读取存储在存储器中的信息，并且可靠地设置锁存电路中的信息。
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公开(公告)号：US20050254316A1
公开(公告)日：2005-11-17
申请号：US11127712
申请日：2005-05-12
摘要： The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.
摘要翻译： 半导体器件包括：存储单元阵列，其包括用于存储数据的存储单元，并以扇区为基础进行管理;存储器，其存储确定激活状态的信息;锁存电路，其根据存储在存储器中的信息来锁存激活信息 以及根据存储在锁存电路中的存储器中的信息来锁存激活信息的电路。 根据存储器的存储状态的激活信息在激活之后输入给定命令时被锁存，因此可以读取存储在存储器中的信息，并且可靠地设置锁存电路中的信息。
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公开(公告)号：US20050254329A1
公开(公告)日：2005-11-17
申请号：US11126738
申请日：2005-05-11
CPC分类号： G11C16/12
摘要： The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to simultaneously program multiple bits in the memory cells of the selected page, when the multiple bits are programmed in the multiple pages. The page is a selection unit and is composed of a given number of the memory cells located on a same word line. An unnecessary stress of programming is not applied to the memory cells that are not to be programmed, by increasing the distance between the memory cells to be programmed simultaneously.
摘要翻译： 本发明的半导体器件包括列解码器（选择和写入电路），其选择彼此不相邻的多个页面，以便当多位数据同时编程所选页面的存储器单元中的多个位时 在多页中编程。 该页面是选择单元，并且由位于相同字线上的给定数量的存储器单元组成。 通过增加要同时编程的存储单元之间的距离，不会对不需要编程的存储单元施加不必要的编程压力。
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公开(公告)号：US07221587B2
公开(公告)日：2007-05-22
申请号：US11126738
申请日：2005-05-11
CPC分类号： G11C16/12
摘要： The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to simultaneously program multiple bits in the memory cells of the selected page, when the multiple bits are programmed in the multiple pages. The page is a selection unit and is composed of a given number of the memory cells located on a same word line. An unnecessary stress of programming is not applied to the memory cells that are not to be programmed, by increasing the distance between the memory cells to be programmed simultaneously.
摘要翻译： 本发明的半导体器件包括列解码器（选择和写入电路），其选择彼此不相邻的多个页面，以便当多位数据同时编程所选页面的存储器单元中的多个位时 在多页中编程。 该页面是选择单元，并且由位于相同字线上的给定数量的存储器单元组成。 通过增加要同时编程的存储单元之间的距离，不会对不需要编程的存储单元施加不必要的编程压力。
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公开(公告)号：US08379472B2
公开(公告)日：2013-02-19
申请号：US13155278
申请日：2011-06-07
申请人： Hiroaki Wada , Kazuhiro Kurihara
发明人： Hiroaki Wada , Kazuhiro Kurihara
IPC分类号： G11C5/14
CPC分类号： G11C16/30 , G11C5/147 , H04N5/23241
摘要： The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.
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公开(公告)号：US07957205B2
公开(公告)日：2011-06-07
申请号：US12574413
申请日：2009-10-06
申请人： Hiroaki Wada , Kazuhiro Kurihara
发明人： Hiroaki Wada , Kazuhiro Kurihara
IPC分类号： G11C5/14
CPC分类号： G11C16/30 , G11C5/147 , H04N5/23241
摘要： The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.
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