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公开(公告)号：US07221587B2
公开(公告)日：2007-05-22
申请号：US11126738
申请日：2005-05-11
CPC分类号： G11C16/12
摘要： The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to simultaneously program multiple bits in the memory cells of the selected page, when the multiple bits are programmed in the multiple pages. The page is a selection unit and is composed of a given number of the memory cells located on a same word line. An unnecessary stress of programming is not applied to the memory cells that are not to be programmed, by increasing the distance between the memory cells to be programmed simultaneously.
摘要翻译： 本发明的半导体器件包括列解码器（选择和写入电路），其选择彼此不相邻的多个页面，以便当多位数据同时编程所选页面的存储器单元中的多个位时 在多页中编程。 该页面是选择单元，并且由位于相同字线上的给定数量的存储器单元组成。 通过增加要同时编程的存储单元之间的距离，不会对不需要编程的存储单元施加不必要的编程压力。
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公开(公告)号：US20050276125A1
公开(公告)日：2005-12-15
申请号：US11126869
申请日：2005-05-11
CPC分类号： G11C16/08 , G06F12/1425 , G11C16/22 , Y02D10/13
摘要： A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.
摘要翻译： 一种半导体器件包括：第一存储单元阵列，其包括用于存储数据的存储器单元，并以扇区为基础进行管理;第二存储单元阵列，包括存储器单元，该存储单元存储基于扇区的扇区保护信息;以及控制电路，检查扇区保护信息 每当选择要编程或擦除的扇区时，存储在第二存储单元阵列中。 因此，所有扇区中的扇区保护信息在上电时不必被锁存。 不必提供与扇区数量相等的锁存电路。 因此可以大大减少电路的数量，并且可以减小芯片面积。
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3.发明授权Semiconductor memory device and control method having data protection feature 有权具有数据保护特性的半导体存储器件和控制方法公开(公告)号：US07224602B2
公开(公告)日：2007-05-29
申请号：US11126869
申请日：2005-05-11
CPC分类号： G11C16/08 , G06F12/1425 , G11C16/22 , Y02D10/13
摘要： A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.
摘要翻译： 一种半导体器件包括：第一存储单元阵列，其包括用于存储数据的存储器单元，并以扇区为基础进行管理;第二存储单元阵列，包括存储器单元，该存储单元存储基于扇区的扇区保护信息;以及控制电路，检查扇区保护信息 每当选择要编程或擦除的扇区时，存储在第二存储单元阵列中。 因此，所有扇区中的扇区保护信息在上电时不必被锁存。 不必提供与扇区数量相等的锁存电路。 因此可以大大减少电路的数量，并且可以减小芯片面积。
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公开(公告)号：US20050276112A1
公开(公告)日：2005-12-15
申请号：US11126558
申请日：2005-05-11
CPC分类号： G11C16/12 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3445 , G11C16/3459
摘要： The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.
摘要翻译： 本发明的半导体器件包括至少一个编程状态的虚拟单元，其近似位于参考单元阵列的边缘。 因此，当读取参考单元阵列的边缘上的单元的数据时，泄漏电流不流动。 位于参考单元阵列中心周围的存储单元具有编程状态的相邻单元，并且当从所有参考单元读出数据时，可以防止泄漏电流。 因此，能够稳定地供给基准电流。
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公开(公告)号：US20050254329A1
公开(公告)日：2005-11-17
申请号：US11126738
申请日：2005-05-11
CPC分类号： G11C16/12
摘要： The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to simultaneously program multiple bits in the memory cells of the selected page, when the multiple bits are programmed in the multiple pages. The page is a selection unit and is composed of a given number of the memory cells located on a same word line. An unnecessary stress of programming is not applied to the memory cells that are not to be programmed, by increasing the distance between the memory cells to be programmed simultaneously.
摘要翻译： 本发明的半导体器件包括列解码器（选择和写入电路），其选择彼此不相邻的多个页面，以便当多位数据同时编程所选页面的存储器单元中的多个位时 在多页中编程。 该页面是选择单元，并且由位于相同字线上的给定数量的存储器单元组成。 通过增加要同时编程的存储单元之间的距离，不会对不需要编程的存储单元施加不必要的编程压力。
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公开(公告)号：US07206241B2
公开(公告)日：2007-04-17
申请号：US11126558
申请日：2005-05-11
IPC分类号： G11C7/02
CPC分类号： G11C16/12 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3445 , G11C16/3459
摘要： The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.
摘要翻译： 本发明的半导体器件包括至少一个编程状态的虚拟单元，其近似位于参考单元阵列的边缘。 因此，当读取参考单元阵列的边缘上的单元的数据时，泄漏电流不流动。 位于参考单元阵列中心周围的存储单元具有编程状态的相邻单元，并且当从所有参考单元读出数据时，可以防止泄漏电流。 因此，能够稳定地供给基准电流。
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公开(公告)号：US07307894B2
公开(公告)日：2007-12-11
申请号：US11127712
申请日：2005-05-12
IPC分类号： G11C7/10
摘要： The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.
摘要翻译： 半导体器件包括：存储单元阵列，其包括用于存储数据的存储单元，并以扇区为基础进行管理;存储器，其存储确定激活状态的信息;锁存电路，其根据存储在存储器中的信息来锁存激活信息 以及根据存储在锁存电路中的存储器中的信息来锁存激活信息的电路。 根据存储器的存储状态的激活信息在激活之后输入给定命令时被锁存，因此可以读取存储在存储器中的信息，并且可靠地设置锁存电路中的信息。
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公开(公告)号：US20050254316A1
公开(公告)日：2005-11-17
申请号：US11127712
申请日：2005-05-12
摘要： The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.
摘要翻译： 半导体器件包括：存储单元阵列，其包括用于存储数据的存储单元，并以扇区为基础进行管理;存储器，其存储确定激活状态的信息;锁存电路，其根据存储在存储器中的信息来锁存激活信息 以及根据存储在锁存电路中的存储器中的信息来锁存激活信息的电路。 根据存储器的存储状态的激活信息在激活之后输入给定命令时被锁存，因此可以读取存储在存储器中的信息，并且可靠地设置锁存电路中的信息。
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9.发明申请Aluminum alloy, cast article of aluminum alloy, and method for producing cast article of aluminum alloy 审中-公开铝合金，铝合金铸件和铝合金铸造件的制造方法公开(公告)号：US20050000604A1
公开(公告)日：2005-01-06
申请号：US10487940
申请日：2002-08-30
申请人： Hiroshi Kawahara , Yoshihiro Shimizu , Yoshio Sugiyama , Toshio Horie , Hiroaki Iwahori , Yoshihiko Sugimoto , Minoru Yamashita
发明人： Hiroshi Kawahara , Yoshihiro Shimizu , Yoshio Sugiyama , Toshio Horie , Hiroaki Iwahori , Yoshihiko Sugimoto , Minoru Yamashita
CPC分类号： C22C21/06 , B22D21/007
摘要： An aluminum alloy according to the present invention includes from 4.0 to 6.0% Mg, from 0.3 to 0.6% Mn, from 0.5 to 0.9% Fe, and the balance of Al and inevitable impurities when the entirety is taken as 100% by mass. By appropriately selecting the composition range of Mg, Mn and Fe, it has been possible to micro-finely crystallize Al (Mn, Fe) compounds while inhibiting the growth of primary-crystal Al. As a result, the resulting aluminum alloy is good in terms of the castability, and shows high strength as well as high ductility.
摘要翻译： 本发明的铝合金包含4.0〜6.0％的Mg，0.3〜0.6％的Mn，0.5〜0.9％的Fe，当全部为100质量％时，其余为Al和不可避免的杂质。 通过适当选择Mg，Mn和Fe的组成范围，可以在抑制一次晶体Al的生长的同时微细微细化Al（Mn，Fe）化合物。 结果，所得铝合金在铸造性方面是良好的，并且显示出高强度以及高延展性。
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10.发明授权
公开(公告)号：US6014329A
公开(公告)日：2000-01-11
申请号：US986337
申请日：1997-12-05
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译： 闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制 电路提供写入控制信号时，写入信息。 写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。 此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。
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