公开(公告)号：US08435417B2

公开(公告)日：2013-05-07

申请号：US12827259

申请日：2010-06-30

申请人： Kazunari Nakata ,  Kaoru Motonami ,  Atsushi Narazaki ,  Ayumu Onoyama ,  Shigeto Honda ,  Ryoichi Fujii ,  Tomoya Hirata

发明人： Kazunari Nakata ,  Kaoru Motonami ,  Atsushi Narazaki ,  Ayumu Onoyama ,  Shigeto Honda ,  Ryoichi Fujii ,  Tomoya Hirata

IPC分类号： B44C1/22

CPC分类号： H01L21/3083 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/30105 ,  H01L2924/00

摘要： A passivation film having a predetermined width from an outer peripheral end portion toward an inner side and extending along the outer peripheral end portion is formed on a front surface of a semiconductor substrate. An outer peripheral end surface orthogonal to the front surface and a rear surface is formed by grinding the outer peripheral end portion of the semiconductor substrate. A thickness of the semiconductor substrate is reduced to a predetermined thickness by grinding the rear surface. The ground rear surface is etched by discharging a mixed acid onto the rear surface while rotating the semiconductor substrate with the rear surface facing upward, to remove a fracture layer. Thereby, chipping or cracking of the semiconductor substrate is suppressed.

摘要翻译： 在半导体衬底的前表面上形成有从外周端向内侧具有预定宽度且沿外周端部延伸的钝化膜。 通过研磨半导体衬底的外周端部形成与前表面和后表面正交的外周端面。 通过研磨后表面将半导体衬底的厚度减小到预定厚度。 通过将混合酸排放到后表面上同时使后表面朝上的半导体衬底旋转来蚀刻地面后表面，以除去断裂层。 由此，能够抑制半导体基板的切削或破裂。

公开(公告)号：US08247867B2

公开(公告)日：2012-08-21

申请号：US12836922

申请日：2010-07-15

申请人： Kazunari Nakata ,  Atsushi Narazaki ,  Shigeto Honda ,  Kaoru Motonami

发明人： Kazunari Nakata ,  Atsushi Narazaki ,  Shigeto Honda ,  Kaoru Motonami

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a base layer that has a first conductivity type, a source layer that is formed on the base layer and has a second conductivity type, and an insulating film that is formed on the source layer. The semiconductor device further includes a plurality of gate structures that penetrate the base layer, and a plurality of conductive parts that penetrate the insulating film and the source layer and electrically connect the source layer and the base layer to each other. The gate structures are formed in a stripe shape in plan view. Parts in which the conductive portion is connected to the base layer are formed in a stripe shape in plan view, and are formed between the gate structures. Further, a dimension of the part in which the source layer and the base layer are in contact with each other between the gate structure and the conductive portion is 0.36 μm or more.

摘要翻译： 半导体器件包括具有第一导电类型的基极层，形成在基极层上并具有第二导电类型的源极层，以及形成在源极层上的绝缘膜。 半导体器件还包括穿透基底层的多个栅极结构，以及穿透绝缘膜和源极层并将源极层和基极层彼此电连接的多个导电部件。 栅极结构在平面图中形成为条状。 导电部分连接到基底层的部分在平面图中形成为条形，并且形成在栅极结构之间。 此外，栅极结构和导电部之间的源极层和基极层彼此接触的部分的尺寸为0.36μm以上。

公开(公告)号：US20110059612A1

公开(公告)日：2011-03-10

申请号：US12827259

申请日：2010-06-30

申请人： Kazunari NAKATA ,  Kaoru Motonami ,  Atsushi Narazaki ,  Ayumu Onoyama ,  Shigeto Honda ,  Ryoichi Fujii ,  Tomoya Hirata

发明人： Kazunari NAKATA ,  Kaoru Motonami ,  Atsushi Narazaki ,  Ayumu Onoyama ,  Shigeto Honda ,  Ryoichi Fujii ,  Tomoya Hirata

IPC分类号： H01L21/302

CPC分类号： H01L21/3083 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/30105 ,  H01L2924/00

摘要： A passivation film having a predetermined width from an outer peripheral end portion toward an inner side and extending along the outer peripheral end portion is formed on a front surface of a semiconductor substrate. An outer peripheral end surface orthogonal to the front surface and a rear surface is formed by grinding the outer peripheral end portion of the semiconductor substrate. A thickness of the semiconductor substrate is reduced to a predetermined thickness by grinding the rear surface. The ground rear surface is etched by discharging a mixed acid onto the rear surface while rotating the semiconductor substrate with the rear surface facing upward, to remove a fracture layer. Thereby, chipping or cracking of the semiconductor substrate is suppressed.

摘要翻译： 在半导体衬底的前表面上形成有从外周端向内侧具有预定宽度且沿外周端部延伸的钝化膜。 通过研磨半导体衬底的外周端部形成与前表面和后表面正交的外周端面。 通过研磨后表面将半导体衬底的厚度减小到预定厚度。 通过将混合酸排放到后表面上同时使后表面朝上的半导体衬底旋转来蚀刻地面后表面，以除去断裂层。 由此，能够抑制半导体基板的切削或破裂。

公开(公告)号：US20110089487A1

公开(公告)日：2011-04-21

申请号：US12836922

申请日：2010-07-15

申请人： Kazunari NAKATA ,  Atsushi Narazaki ,  Shigeto Honda ,  Kaoru Motonami

发明人： Kazunari NAKATA ,  Atsushi Narazaki ,  Shigeto Honda ,  Kaoru Motonami

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a base layer that has a first conductivity type, a source layer that is formed on the base layer and has a second conductivity type, and an insulating film that is formed on the source layer. The semiconductor device further includes a plurality of gate structures that penetrate the base layer, and a plurality of conductive parts that penetrate the insulating film and the source layer and electrically connect the source layer and the base layer to each other. The gate structures are formed in a strip shape in plan view. Parts in which the conductive portion is connected to the base layer are formed in a stripe shape in plan view, and are formed between the gate structures. Further, a dimension of the part in which the source layer and the base layer are in contact with each other between the gate structure and the conductive portion is 0.36 μm or more.

摘要翻译： 半导体器件包括具有第一导电类型的基极层，形成在基极层上并具有第二导电类型的源极层，以及形成在源极层上的绝缘膜。 半导体器件还包括穿透基底层的多个栅极结构，以及穿透绝缘膜和源极层并将源极层和基极层彼此电连接的多个导电部件。 栅极结构在平面图中形成为带状。 导电部分连接到基底层的部分在平面图中形成为条形，并且形成在栅极结构之间。 此外，栅极结构和导电部之间的源极层和基极层彼此接触的部分的尺寸为0.36μm以上。

公开(公告)号：US20110220914A1

公开(公告)日：2011-09-15

申请号：US12961905

申请日：2010-12-07

申请人： Ryoichi Fujii ,  Shigeto Honda ,  Atsushi Narazaki ,  Kaoru Motonami

发明人： Ryoichi Fujii ,  Shigeto Honda ,  Atsushi Narazaki ,  Kaoru Motonami

IPC分类号： H01L29/66 ,  H01L21/302

CPC分类号： H01L29/063 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 6; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.

摘要翻译： 根据本发明的制造功率半导体器件的方法包括以下步骤：（a）在半导体衬底上形成氮化硅膜; （b）在步骤（a）之后，沿着半导体衬底6的周边部分形成环形沟槽; （c）在所述沟槽的内表面上形成第一氧化硅膜; （d）在步骤（c）之后，在半导体衬底的整个表面上形成第二氧化硅膜以埋置沟槽; （e）通过使用氮化硅膜作为塞子来平坦化第二氧化硅膜; 和（f）在除去氮化硅膜的区域中形成第三氧化硅膜。

公开(公告)号：US08450183B2

公开(公告)日：2013-05-28

申请号：US12961905

申请日：2010-12-07

申请人： Ryoichi Fujii ,  Shigeto Honda ,  Atsushi Narazaki ,  Kaoru Motonami

发明人： Ryoichi Fujii ,  Shigeto Honda ,  Atsushi Narazaki ,  Kaoru Motonami

IPC分类号： H01L21/76 ,  H01L31/0312 ,  H01L23/58

CPC分类号： H01L29/063 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 6; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.

摘要翻译： 根据本发明的制造功率半导体器件的方法包括以下步骤：（a）在半导体衬底上形成氮化硅膜; （b）在步骤（a）之后，沿着半导体衬底6的周边部分形成环形沟槽; （c）在所述沟槽的内表面上形成第一氧化硅膜; （d）在步骤（c）之后，在半导体衬底的整个表面上形成第二氧化硅膜以埋置沟槽; （e）通过使用氮化硅膜作为塞子来平坦化第二氧化硅膜; 和（f）在除去氮化硅膜的区域中形成第三氧化硅膜。

公开(公告)号：US09431479B2

公开(公告)日：2016-08-30

申请号：US12845176

申请日：2010-07-28

申请人： Shigeto Honda ,  Atsushi Narazaki ,  Kaoru Motonami

发明人： Shigeto Honda ,  Atsushi Narazaki ,  Kaoru Motonami

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/861 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78

CPC分类号： H01L29/0615 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66128 ,  H01L29/7811 ,  H01L29/8611

摘要： In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part.

摘要翻译： 在根据本发明的半导体器件中，在半导体衬底的表面上形成电极层和凹部。 此外，在半导体基板中，形成与凹部的底面接触的RESURF层和电极层。 此外，在半导体衬底的上表面上形成绝缘膜以便填充凹部。 此外，在凹部上方的绝缘膜上形成场板电极。

公开(公告)号：US20110084354A1

公开(公告)日：2011-04-14

申请号：US12845176

申请日：2010-07-28

申请人： Shigeto Honda ,  Atsushi Narazaki ,  Kaoru Motonami

发明人： Shigeto Honda ,  Atsushi Narazaki ,  Kaoru Motonami

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L29/0615 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66128 ,  H01L29/7811 ,  H01L29/8611

摘要： In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part.

摘要翻译： 在根据本发明的半导体器件中，在半导体衬底的表面上形成电极层和凹部。 此外，在半导体基板中，形成与凹部的底面接触的RESURF层和电极层。 此外，在半导体衬底的上表面上形成绝缘膜以便填充凹部。 此外，在凹部上方的绝缘膜上形成场板电极。

公开(公告)号：US08552428B2

公开(公告)日：2013-10-08

申请号：US12962079

申请日：2010-12-07

申请人： Shigeto Honda

发明人： Shigeto Honda

IPC分类号： H01L23/58 ,  H01L31/0256 ,  H01L31/0312 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4232 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7395 ,  H01L29/7804 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor device according to the present invention, which has a termination structure in which a field plate is provided on an insulating film filled in a recessed region formed in a semiconductor substrate and includes a plurality of unit cells connected in parallel, includes: a gate wiring region in which gate wiring electrically connected to each gate electrode of the plurality of unit cells is provided; and a gate pad region electrically connected to the gate wiring region, wherein the gate wiring region is disposed on the insulating film filled in a recessed region formed in the semiconductor substrate.

摘要翻译： 根据本发明的功率半导体器件，其具有终端结构，其中场板设置在填充在形成在半导体衬底中的凹陷区域中的绝缘膜上，并且包括并联连接的多个单元电池，包括： 设置与多个单位电池的各个栅电极电连接的栅极配线的栅极配线区域; 以及与所述栅极布线区域电连接的栅极焊盘区域，其中，所述栅极布线区域设置在填充在形成在所述半导体基板中的凹部区域中的所述绝缘膜上。

公开(公告)号：US08614448B2

公开(公告)日：2013-12-24

申请号：US13237577

申请日：2011-09-20

申请人： Shigeto Honda

发明人： Shigeto Honda

IPC分类号： H01L29/15

CPC分类号： H01L29/7395 ,  H01L29/0834 ,  H01L29/36

摘要： A semiconductor device includes a semiconductor substrate having a collector layer in which the carrier concentration is maximized at a carrier concentration peak position that is 1 μm or more from a surface of the semiconductor substrate. The semiconductor device further includes a collector electrode formed in contact with a surface of the collector layer.

摘要翻译： 半导体器件包括具有集电极层的半导体衬底，其中载流子浓度在距离半导体衬底的表面1μm或更大的载流子浓度峰值位置处最大化。 半导体器件还包括与集电极层的表面接触形成的集电极。