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公开(公告)号：US08435417B2
公开(公告)日：2013-05-07
申请号：US12827259
申请日：2010-06-30
申请人： Kazunari Nakata , Kaoru Motonami , Atsushi Narazaki , Ayumu Onoyama , Shigeto Honda , Ryoichi Fujii , Tomoya Hirata
发明人： Kazunari Nakata , Kaoru Motonami , Atsushi Narazaki , Ayumu Onoyama , Shigeto Honda , Ryoichi Fujii , Tomoya Hirata
IPC分类号： B44C1/22
CPC分类号： H01L21/3083 , H01L21/304 , H01L21/6835 , H01L21/6836 , H01L2221/68327 , H01L2221/6834 , H01L2924/0002 , H01L2924/30105 , H01L2924/00
摘要： A passivation film having a predetermined width from an outer peripheral end portion toward an inner side and extending along the outer peripheral end portion is formed on a front surface of a semiconductor substrate. An outer peripheral end surface orthogonal to the front surface and a rear surface is formed by grinding the outer peripheral end portion of the semiconductor substrate. A thickness of the semiconductor substrate is reduced to a predetermined thickness by grinding the rear surface. The ground rear surface is etched by discharging a mixed acid onto the rear surface while rotating the semiconductor substrate with the rear surface facing upward, to remove a fracture layer. Thereby, chipping or cracking of the semiconductor substrate is suppressed.
摘要翻译： 在半导体衬底的前表面上形成有从外周端向内侧具有预定宽度且沿外周端部延伸的钝化膜。 通过研磨半导体衬底的外周端部形成与前表面和后表面正交的外周端面。 通过研磨后表面将半导体衬底的厚度减小到预定厚度。 通过将混合酸排放到后表面上同时使后表面朝上的半导体衬底旋转来蚀刻地面后表面，以除去断裂层。 由此，能够抑制半导体基板的切削或破裂。
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公开(公告)号：US08247867B2
公开(公告)日：2012-08-21
申请号：US12836922
申请日：2010-07-15
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a base layer that has a first conductivity type, a source layer that is formed on the base layer and has a second conductivity type, and an insulating film that is formed on the source layer. The semiconductor device further includes a plurality of gate structures that penetrate the base layer, and a plurality of conductive parts that penetrate the insulating film and the source layer and electrically connect the source layer and the base layer to each other. The gate structures are formed in a stripe shape in plan view. Parts in which the conductive portion is connected to the base layer are formed in a stripe shape in plan view, and are formed between the gate structures. Further, a dimension of the part in which the source layer and the base layer are in contact with each other between the gate structure and the conductive portion is 0.36 μm or more.
摘要翻译： 半导体器件包括具有第一导电类型的基极层，形成在基极层上并具有第二导电类型的源极层，以及形成在源极层上的绝缘膜。 半导体器件还包括穿透基底层的多个栅极结构，以及穿透绝缘膜和源极层并将源极层和基极层彼此电连接的多个导电部件。 栅极结构在平面图中形成为条状。 导电部分连接到基底层的部分在平面图中形成为条形，并且形成在栅极结构之间。 此外，栅极结构和导电部之间的源极层和基极层彼此接触的部分的尺寸为0.36μm以上。
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公开(公告)号：US08993413B2
公开(公告)日：2015-03-31
申请号：US13708358
申请日：2012-12-07
申请人： Kazunari Nakata , Yoshiaki Terasaki
发明人： Kazunari Nakata , Yoshiaki Terasaki
IPC分类号： H01L21/00 , H01L21/02 , H01L21/78 , H01L21/683
CPC分类号： H01L21/02005 , H01L21/6836 , H01L21/78 , H01L2221/68331
摘要： A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.
摘要翻译： 一种制造半导体器件的方法包括以下步骤：制备半导体晶片，该半导体晶片在外周端部具有厚壁部分，在中心部分形成薄壁部分，将支撑材料附着到半导体晶片的一个表面，将半导体晶片 进入厚部分和薄部分，并且在分割之后切割薄部分，同时通过支撑材料支撑薄部分。
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公开(公告)号：US08574962B2
公开(公告)日：2013-11-05
申请号：US13231198
申请日：2011-09-13
申请人： Kazunari Nakata , Yoshiaki Terasaki
发明人： Kazunari Nakata , Yoshiaki Terasaki
IPC分类号： H01L21/00
CPC分类号： H01L29/66333 , H01L21/304 , H01L21/6836 , H01L2221/68327 , H01L2221/6834
摘要： A method of manufacturing a semiconductor device comprises the steps of (a) applying a resin member onto a front surface of a semiconductor wafer having an uneven structure on the front surface thereof, and (b) flattening a surface of the resin member by heating the resin member, and in the method, the resin member is formed also on a side surface of the semiconductor wafer. The method further comprises the steps of (c) performing a thinning process for the semiconductor wafer on a back surface thereof after the step (b), and (d) removing the resin member from the semiconductor wafer after the step (c). By the method, it is possible to uniformize the thickness of a semiconductor wafer which is thinned and reduce the number of foreign matters remaining on a surface of the semiconductor wafer.
摘要翻译： 一种制造半导体器件的方法包括以下步骤：（a）将树脂部件施加到其表面上具有不均匀结构的半导体晶片的正面上，以及（b）通过加热所述树脂部件的表面来使所述树脂部件的表面平坦化 树脂构件，并且在该方法中，树脂构件也形成在半导体晶片的侧表面上。 该方法还包括以下步骤：（c）在步骤（b）之后，在其后表面上对半导体晶片进行稀化处理，和（d）在步骤（c）之后从半导体晶片去除树脂构件。 通过该方法，可以使被稀释的半导体晶片的厚度均匀化并且减少残留在半导体晶片的表面上的异物的数量。
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公开(公告)号：US20130052812A1
公开(公告)日：2013-02-28
申请号：US13453039
申请日：2012-04-23
申请人： Kazunari Nakata , Tamio Matsumura
发明人： Kazunari Nakata , Tamio Matsumura
IPC分类号： H01L21/265 , H01L21/306 , H01L21/31 , H01L21/304 , H01L21/28
CPC分类号： H01L21/304 , B24B7/228 , B24B41/068 , H01L29/0657
摘要： A method of manufacturing a semiconductor device, includes a wafer grinding step of, by means of a revolving grinding stone, forming a thinned portion in a wafer while at the same time forming a slope surrounding said thinned portion, wherein during said formation of said slope, said grinding stone is positioned so that there is always a space between said slope and the facing side of said grinding stone, wherein said thinned portion is thinner than a peripheral portion of said wafer, and wherein said slope extends along and defines an inner circumferential side of said peripheral portion and forms an angle of 75° or more but less than 90° with respect to a main surface of said wafer. The method of manufacturing a semiconductor device further includes a step of forming a semiconductor device in said thinned portion.
摘要翻译： 一种制造半导体器件的方法包括：通过旋转研磨石在晶片中形成薄化部分同时形成围绕所述薄化部分的斜面的晶片研磨步骤，其中在所述斜面的形成期间 所述研磨石的位置使得在所述磨石的所述倾斜面和所述相对侧之间总是具有空间，其中所述变薄部分比所述晶片的周边部分薄，并且其中所述斜面沿着并且限定内圆周 并且相对于所述晶片的主表面形成75°以上但小于90°的角度。 制造半导体器件的方法还包括在所述薄化部分中形成半导体器件的步骤。
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公开(公告)号：US20110309436A1
公开(公告)日：2011-12-22
申请号：US13148326
申请日：2009-04-28
申请人： Kazunari Nakata
发明人： Kazunari Nakata
IPC分类号： H01L29/78
CPC分类号： H01L29/7397 , H01L24/05 , H01L24/45 , H01L24/48 , H01L29/0649 , H01L29/41741 , H01L29/456 , H01L29/7813 , H01L2224/04042 , H01L2224/05073 , H01L2224/05558 , H01L2224/05624 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/4847 , H01L2224/48724 , H01L2224/85205 , H01L2924/0101 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01041 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/00014 , H01L2224/85 , H01L2924/00
摘要： A gate electrode is provided for controlling a current flowing through a semiconductor layer. A gate insulating film electrically insulates the semiconductor layer and the gate electrode from each other. A conductor portion is provided on the semiconductor layer, and electrically connected with the semiconductor layer. An interlayer insulating film is provided on the gate electrode such that the conductor portion is electrically insulated from the gate electrode. A buffer insulating film covers a partial region on the conductor portion and the interlayer insulating film, and is made of an insulator. An electrode layer has a wiring portion located on a region from which the conductor portion is exposed, and a pad portion located on the buffer insulating film. Thereby, damage to an IGBT caused when a wire is connected to the pad portion can be suppressed. Further, larger electric power can be handled, while preventing occurrence of breakage due to current concentration.
摘要翻译： 提供栅电极用于控制流过半导体层的电流。 栅极绝缘膜将半导体层和栅电极彼此电绝缘。 导体部分设置在半导体层上，与半导体层电连接。 在栅电极上设置层间绝缘膜，使得导体部分与栅电极电绝缘。 缓冲绝缘膜覆盖导体部分和层间绝缘膜上的部分区域，并由绝缘体制成。 电极层具有位于导体部分露出的区域上的布线部分和位于缓冲绝缘膜上的焊盘部分。 因此，可以抑制当连接到焊盘部分时引起的对IGBT引起的损坏。 此外，可以处理较大的电力，同时防止由于电流集中而导致的断裂。
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公开(公告)号：US5251631A
公开(公告)日：1993-10-12
申请号：US788473
申请日：1991-11-06
CPC分类号： G01S7/5205 , A61B8/00 , A61B8/4438 , A61B8/585 , G01D18/008 , G01D3/022
摘要： An ultrasonic imaging apparatus comprising the main body containing a transmission system, a reception system composed of a plurality of receiving sections, a signal processing system, a display system, and a first connector, a probe unit containing a plurality of transducers, a second connector for connecting the probe unit to the first connector of the main body in a detachable manner, a memory in stalled in the second connector for storing data to calibrate at least one of the sensitivity and phase characteristics for each of the plurality of transducers, and a calibration circuit installed in the main body for retrieving stored data from the memory and calibrating one of sensitivity and phase characteristics for each of the plurality of receiving sections of the reception system.
摘要翻译： 一种超声波成像装置，包括：包含传输系统的主体，由多个接收部组成的接收系统，信号处理系统，显示系统和第一连接器;包含多个换能器的探针单元;第二连接器 用于以可拆卸的方式将探针单元连接到主体的第一连接器;在第二连接器中停滞的存储器，用于存储用于校准多个换能器中的每一个的灵敏度和相位特性中的至少一个的数据，以及 校准电路安装在主体中用于从存储器检索存储的数据，并且校准接收系统的多个接收部分中的每一个的灵敏度和相位特性之一。
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公开(公告)号：US09324581B2
公开(公告)日：2016-04-26
申请号：US13739946
申请日：2013-01-11
申请人： Kazunari Nakata , Yoshiaki Terasaki
发明人： Kazunari Nakata , Yoshiaki Terasaki
IPC分类号： H01L21/50 , H01L21/67 , H01L21/683
CPC分类号： H01L21/50 , H01L21/67115 , H01L21/67132 , H01L21/6836 , H01L2221/68327 , H01L2221/6834
摘要： A wafer is mounted to a dicing frame using a holding tape. A plurality of semiconductor devices are provided on a center portion of a major surface of the wafer. A ring-like reinforcing section is provided on a periphery of the major surface. The holding tape is adhered to the major surface The holding tape is heated to at least 0.6 times of melting temperature of the holding tape so as to adhere the holding tape along a step of the ring-like reinforcing section.
摘要翻译： 使用保持带将晶片安装到切割框架。 在晶片的主表面的中心部分设置多个半导体器件。 在主表面的周围设有环状的加强部。 保持带粘附到主表面上。将保持带加热至保持带的熔融温度的至少0.6倍，以便沿着环状加强部的台阶粘合保持带。
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公开(公告)号：US08987122B2
公开(公告)日：2015-03-24
申请号：US13453039
申请日：2012-04-23
申请人： Kazunari Nakata , Tamio Matsumura
发明人： Kazunari Nakata , Tamio Matsumura
IPC分类号： H01L29/30 , H01L21/304 , B24B41/06 , B24B7/22 , H01L29/06
CPC分类号： H01L21/304 , B24B7/228 , B24B41/068 , H01L29/0657
摘要： A method of manufacturing a semiconductor device, includes a wafer grinding step of, by means of a revolving grinding stone, forming a thinned portion in a wafer while at the same time forming a slope surrounding said thinned portion, wherein during said formation of said slope, said grinding stone is positioned so that there is always a space between said slope and the facing side of said grinding stone, wherein said thinned portion is thinner than a peripheral portion of said wafer, and wherein said slope extends along and defines an inner circumferential side of said peripheral portion and forms an angle of 75° or more but less than 90° with respect to a main surface of said wafer. The method of manufacturing a semiconductor device further includes a step of forming a semiconductor device in said thinned portion.
摘要翻译： 一种制造半导体器件的方法包括：通过旋转研磨石在晶片中形成薄化部分同时形成围绕所述薄化部分的斜面的晶片研磨步骤，其中在所述斜面的形成期间 所述研磨石的位置使得在所述磨石的所述倾斜面和所述相对侧之间总是具有空间，其中所述变薄部分比所述晶片的周边部分薄，并且其中所述斜面沿着并且限定内圆周 并且相对于所述晶片的主表面形成75°以上但小于90°的角度。 制造半导体器件的方法还包括在所述薄化部分中形成半导体器件的步骤。
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公开(公告)号：US20130203241A1
公开(公告)日：2013-08-08
申请号：US13708358
申请日：2012-12-07
申请人： Kazunari Nakata , Yoshiaki Terasaki
发明人： Kazunari Nakata , Yoshiaki Terasaki
IPC分类号： H01L21/02
CPC分类号： H01L21/02005 , H01L21/6836 , H01L21/78 , H01L2221/68331
摘要： A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.
摘要翻译： 一种制造半导体器件的方法包括以下步骤：制备半导体晶片，该半导体晶片在外周端部具有厚壁部分，在中心部分形成薄壁部分，将支撑材料附着到半导体晶片的一个表面，将半导体晶片 进入厚部分和薄部分，并且在分割之后切割薄部分，同时通过支撑材料支撑薄部分。
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