公开(公告)号：US4508851A

公开(公告)日：1985-04-02

申请号：US506269

申请日：1983-06-21

申请人： Kazuo Izumi ,  Kenji Shimazaki ,  Kenji Seki

发明人： Kazuo Izumi ,  Kenji Shimazaki ,  Kenji Seki

IPC分类号： D06M11/00 ,  B01D53/70 ,  B01J20/20 ,  C01B31/08 ,  D01F9/12 ,  D01F9/22 ,  D01F11/12 ,  D01F11/14 ,  D06M11/11 ,  D06M11/55 ,  D06M11/64 ,  D06M11/70 ,  D06M13/188 ,  D06M13/192 ,  D06M23/00 ,  D06M101/00 ,  D06M101/16 ,  D06M101/18 ,  D06M101/28 ,  D06M101/40 ,  C01B31/12

CPC分类号： C01B31/089 ,  D01F11/121 ,  D01F11/14 ,  D01F9/22

摘要： Fibrous activated carbon having a pH not more than 5 which is suitable for recovering halogenated hydrocarbon solvents is disclosed. The fibrous activated carbon is obtained by acid treating raw fibrous activated carbon.

摘要翻译： 公开了适用于回收卤代烃溶剂的pH不大于5的纤维活性炭。 纤维状活性炭通过酸处理原纤维状活性炭而得到。

公开(公告)号：US4412937A

公开(公告)日：1983-11-01

申请号：US371164

申请日：1982-04-23

申请人： Shigeru Ikegami ,  Minoru Hirai ,  Kazuo Izumi ,  Kenji Shimazaki

发明人： Shigeru Ikegami ,  Minoru Hirai ,  Kazuo Izumi ,  Kenji Shimazaki

IPC分类号： C01B31/08 ,  D01F9/22 ,  B01J37/28 ,  B01J37/00 ,  D01F9/12

CPC分类号： D01F9/22 ,  C01B31/089

摘要： A method for manufacturing activated carbon fibers is disclosed. The method is comprised of the steps of:(1) causing an acrylic fiber to contain therein a treating agent selected from the group consisting of phosphorus and boron compounds in a concentration of 0.01 to 0.3% by weight as phosphorus or boron based on the weight of the fiber;(2) preoxidizing the acrylic fiber in an oxidizing atmosphere at a temperature exceeding 200.degree. C. and giving a core ratio of 18% until the amount of bonded oxygen becomes not less than 15% by weight based on the weight of the fiber thereby producing a preoxidized fiber;(3) adjusting the concentration of the treating agent in the preoxidized fiber to a level in the range of 0.04 to 1% by weight based on the thus obtained preoxidized fiber; and(4) thereafter activating the fiber at a temperature in the range of 900.degree. to 1,300.degree. C. The resulting fiber has improved high strength, high adsorbing ability and high processibility.

摘要翻译： 公开了一种制造活性炭纤维的方法。 该方法包括以下步骤：（1）使丙烯酸纤维含有选自磷和硼化合物的处理剂，其浓度为0.01至0.3重量％，作为磷或硼，基于重量 的纤维; （2）在超过200℃的氧化气氛中对丙烯酸类纤维进行预氧化，得到纤芯率为18％，直至接合氧量相对于纤维重量为15重量％以上，由此生成 预氧化纤维; （3）基于由此获得的预氧化纤维，将预氧化纤维中的处理剂的浓度调节至0.04至1重量％范围内的水平; （4）此后在900〜1300℃的温度下活化纤维。所得纤维具有改善的高强度，高吸附能力和高加工性。

公开(公告)号：US4520623A

公开(公告)日：1985-06-04

申请号：US514898

申请日：1983-07-18

申请人： Hiroyasu Ogawa ,  Kazuo Izumi ,  Kenji Shimazaki

发明人： Hiroyasu Ogawa ,  Kazuo Izumi ,  Kenji Shimazaki

IPC分类号： D02G3/16 ,  B01J20/28 ,  C01B31/08 ,  D01F9/22 ,  D02G3/02

CPC分类号： D01F9/22 ,  Y10T428/2918

摘要： An activated carbon fiber spun yarn having excellent workability and adsorptive property is disclosed. The activated carbon fiber spun yarn comprising activated carbon fibers having a specific surface area of 500 to 1,500 m.sup.2 /g, a ductility of at least 0.5%, and a tensile strength of at least 10 kg/mm.sup.2 and derived from acrylonitrile-based fibers. The spun yarn has a twist coefficient of 30 to 60.

摘要翻译： 公开了一种具有优异的加工性和吸附性能的活性炭纤维纱。 活性炭纤维细纱包含比表面积为500〜1500m2 / g，延展性为0.5％以上的活性炭纤维，拉伸强度为10kg / mm 2以上，来自丙烯腈系纤维。 纺纱的扭曲系数为30〜60。

公开(公告)号：US08525552B2

公开(公告)日：2013-09-03

申请号：US13562144

申请日：2012-07-30

申请人： Takashi Ando ,  Keiichi Kusumoto ,  Kenji Shimazaki ,  Kazuyuki Nakanishi ,  Tetsurou Toubou

发明人： Takashi Ando ,  Keiichi Kusumoto ,  Kenji Shimazaki ,  Kazuyuki Nakanishi ,  Tetsurou Toubou

IPC分类号： H01L25/00 ,  H01L21/82 ,  H03K19/00 ,  H03K19/094

CPC分类号： H01L27/0207 ,  H01L27/11807 ,  H01L2027/11822

摘要： A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.

摘要翻译： 半导体集成电路器件包括具有相同逻辑的单元A-1，B-1和C-1。 单元B-1具有大于单元A-1的单元宽度的单元宽度W2，但是MOS晶体管的栅极长度L1等于单元A-1的单元宽度。 单元C-1具有等于单元B-1的单元宽度的单元宽度W2，但是具有栅极长度L2大的MOS晶体管。 与电池A-1和B-1相比，电池C-1的电路延迟变大，但泄漏电流变小。 因此，通过用小区B-1替换与空间区域相邻的小区A-1，并且例如通过用小区C-1定时的具有空间的路径替换小区B-1，可以抑制泄漏电流而不增加 芯片面积。

公开(公告)号：US20070187777A1

公开(公告)日：2007-08-16

申请号：US11783465

申请日：2007-04-10

申请人： Mitsumi Itoh ,  Masatoshi Sawada ,  Junko Honma ,  Kenji Shimazaki ,  Hiroyuki Tsujikawa ,  Hiroshi Benno

发明人： Mitsumi Itoh ,  Masatoshi Sawada ,  Junko Honma ,  Kenji Shimazaki ,  Hiroyuki Tsujikawa ,  Hiroshi Benno

IPC分类号： H01L29/76 ,  G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5068

摘要： It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.

摘要翻译： 本发明的目的是有效地吸收电力噪声并实现电路的稳定操作。 本发明提供了一种半导体器件，包括：旁路电容器，其包括具有形成为从电力布线区域延伸到与电力布线区域相邻的空白区域下方的部分的MOS电结构，并且不具有其他功能层， 并且通过在一个导电类型的扩散区域上的电容绝缘膜形成，以及形成在接地布线区域下方并固定衬底电位的衬底接触，其中旁路电容器具有与形成的电源布线接触的接触 在栅电极的表面上形成具有一个导电类型的扩散区域和基板接触的扩散区域彼此连接。

公开(公告)号：US07779376B2

公开(公告)日：2010-08-17

申请号：US11907166

申请日：2007-10-10

申请人： Shingo Miyahara ,  Kenji Shimazaki

发明人： Shingo Miyahara ,  Kenji Shimazaki

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  G06F2217/78

摘要： Operation analysis is performed for a semiconductor integrated circuit designed by using substrate bias control technology. Power supply potential and substrate potential are analyzed by using circuit information of the semiconductor integrated circuit, and from obtained power supply potential waveform information and substrate potential waveform information, potential difference information indicating a difference value between the power supply potential and the substrate potential is obtained. On the basis of this potential difference information, effects on circuit delay due to substrate noise are analyzed using a delay library showing a relationship between the difference value and the effects on circuit delay. Further, a determination is performed as to whether the difference value exceeds a predetermined difference restriction value.

摘要翻译： 对使用基板偏置控制技术设计的半导体集成电路进行操作分析。 通过使用半导体集成电路的电路信息来分析电源电位和衬底电位，并且从获得的电源电位波形信息和衬底电位波形信息中获得表示电源电位和衬底电位之间的差值的电位差信息 。 基于该电位差信息，使用延迟库来分析由于衬底噪声引起的对电路延迟的影响，该延迟库表示差值与对电路延迟的影响之间的关系。 此外，执行差分值是否超过预定的差异限制值的确定。

公开(公告)号：US20080092090A1

公开(公告)日：2008-04-17

申请号：US11907166

申请日：2007-10-10

申请人： Shingo Miyahara ,  Kenji Shimazaki

发明人： Shingo Miyahara ,  Kenji Shimazaki

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  G06F2217/78

摘要： Operation analysis is performed for a semiconductor integrated circuit designed by using substrate bias control technology. Power supply potential and substrate potential are analyzed by using circuit information of the semiconductor integrated circuit, and from obtained power supply potential waveform information and substrate potential waveform information, potential difference information indicating a difference value between the power supply potential and the substrate potential is obtained. On the basis of this potential difference information, effects on circuit delay due to substrate noise are analyzed using a delay library showing a relationship between the difference value and the effects on circuit delay. Further, a determination is performed as to whether the difference value exceeds a predetermined difference restriction value.

摘要翻译： 对使用基板偏置控制技术设计的半导体集成电路进行操作分析。 通过使用半导体集成电路的电路信息来分析电源电位和衬底电位，并且从获得的电源电位波形信息和衬底电位波形信息中获得表示电源电位和衬底电位之间的差值的电位差信息 。 基于该电位差信息，使用延迟库来分析由于衬底噪声引起的对电路延迟的影响，该延迟库表示差值与对电路延迟的影响之间的关系。 此外，执行差分值是否超过预定的差异限制值的确定。

公开(公告)号：US20060091550A1

公开(公告)日：2006-05-04

申请号：US11231810

申请日：2005-09-22

申请人： Kenji Shimazaki ,  Kazuhiro Satoh ,  Hiroyuki Tsujikawa ,  Shouzou Hirano ,  Makoto Nagata

发明人： Kenji Shimazaki ,  Kazuhiro Satoh ,  Hiroyuki Tsujikawa ,  Shouzou Hirano ,  Makoto Nagata

IPC分类号： H01L23/52

CPC分类号： G06F17/5031

摘要： In a method of analyzing a power noise based on the circuit information of a semiconductor integrated circuit device, the power noise is analyzed in consideration of the influence of the impedance of a substrate. Consequently, the impedance of the substrate which has not been conventionally considered is taken into consideration. Thus, precision in the analysis can be enhanced more greatly.

摘要翻译： 在基于半导体集成电路器件的电路信息分析功率噪声的方法中，考虑到衬底的阻抗的影响来分析功率噪声。 因此，考虑到未经常考虑的基板的阻抗。 因此，分析的精度可以更大的提高。

公开(公告)号：US06959250B1

公开(公告)日：2005-10-25

申请号：US09615938

申请日：2000-07-13

申请人： Kenji Shimazaki ,  Hiroyuki Tsujikawa ,  Seijirou Kojima ,  Shouzou Hirano

发明人： Kenji Shimazaki ,  Hiroyuki Tsujikawa ,  Seijirou Kojima ,  Shouzou Hirano

IPC分类号： G01R29/08 ,  G01R23/00 ,  G01R23/04 ,  G06F17/50 ,  H01L29/00

CPC分类号： G06F17/5036 ,  Y02T10/82

摘要： In contrast with a known dynamic gate-level simulation method, a method of analyzing electromagnetic interference (an EMI analysis method) according to the present invention enables estimation of EMI noise, by means of calculating signal propagation of each node through use of the signal propagation probability technique, and calculating variation time of each node through use of “the Static timing analysis technique”. In short, the present invention is characterized in calculating a frequency characteristic from the relationship between toggle probability of each node and delay in each node.

摘要翻译： 与已知的动态门级仿真方法相反，根据本发明的分析电磁干扰（EMI分析方法）的方法能够通过使用信号传播来计算每个节点的信号传播来估计EMI噪声 概率技术，并通过使用“静态时序分析技术”来计算每个节点的变化时间。 简而言之，本发明的特征在于根据每个节点的触发概率与每个节点的延迟之间的关系来计算频率特性。

公开(公告)号：US20050177334A1

公开(公告)日：2005-08-11

申请号：US11052788

申请日：2005-02-09

申请人： Shozo Hirano ,  Kenji Shimazaki

发明人： Shozo Hirano ,  Kenji Shimazaki

IPC分类号： G06F17/50 ,  G01R27/02 ,  G01R31/00 ,  H01L21/82 ,  G06F19/00

CPC分类号： G06F17/5036

摘要： The resistance value of a supply line (Rline), the resistance value of a decoupling capacitor (Rcap), and the resistance value of a transistor (Rmos) are separately calculated from mask layout information 31 of a semiconductor integrated circuit. The resistance value between external terminals (Ri) is calculated from the resistance value Rline, the resistance value Rcap, and the resistance value Rmos.

摘要翻译： 根据半导体集成电路的掩模布局信息31分别计算供给线的电阻值（Rline），去耦电容器的电阻值（Rcap）和晶体管的电阻值（Rmos）。 根据电阻值Rline，电阻值Rcap和电阻值Rmos计算外部端子（Ri）之间的电阻值。