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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06914294B2

    公开(公告)日：2005-07-05

    申请号：US10438069

    申请日：2003-05-15

    申请人： Kazutoshi Nakamura ,  Tomoko Matsudai ,  Yusuke Kawaguchi ,  Akio Nakagawa

    发明人： Kazutoshi Nakamura ,  Tomoko Matsudai ,  Yusuke Kawaguchi ,  Akio Nakagawa

    IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L31/113

    CPC分类号： H01L29/7835 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7801

    摘要： A semiconductor device comprises a semiconductor substrate having a main surface; a semiconductor layer of a first conduction type provided on the main surface of said semiconductor substrate; a first buried layer of the first conduction type provided between said semiconductor layer and said semiconductor substrate; a first connection region of the first conduction type provided around said first buried layer, said first connection region extending from the surface of said semiconductor layer to said first buried layer; a switching element provided in the surface region of said semiconductor layer on said first buried layer; and a low breakdown-voltage element provided in a surface region of said semiconductor layer, said low breakdown-voltage element being closer to said first connection region than said switching element and having lower breakdown voltage than that of said switching element.

    摘要翻译： 半导体器件包括具有主表面的半导体衬底; 设置在所述半导体衬底的主表面上的第一导电类型的半导体层; 设置在所述半导体层和所述半导体衬底之间的第一导电类型的第一掩埋层; 所述第一导电类型的第一连接区域设置在所述第一掩埋层周围，所述第一连接区域从所述半导体层的表面延伸到所述第一掩埋层; 设置在所述第一掩埋层的所述半导体层的表面区域中的开关元件; 以及设置在所述半导体层的表面区域中的低击穿电压元件，所述低击穿电压元件比所述开关元件更靠近所述第一连接区域，并且具有比所述开关元件的击穿电压低的击穿电压。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06563193B1

    公开(公告)日：2003-05-13

    申请号：US09670548

    申请日：2000-09-27

    申请人： Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Tomoko Matsudai ,  Hirofumi Nagano ,  Akio Nakagawa

    发明人： Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Tomoko Matsudai ,  Hirofumi Nagano ,  Akio Nakagawa

    IPC分类号： H01L27082

    CPC分类号： H01L29/7317 ,  H01L21/76286 ,  H01L21/763 ,  H01L29/735

    摘要： A semiconductor device comprises a substrate the surface of which is formed of an insulation region, a high resistance active layer of a first conductivity type formed on the substrate, a first semiconductor region of the first conductivity type having an impurity concentration higher than that of the active layer and selectively formed on a surface of the active layer, an emitter region of the second conductivity type selectively formed on a surface of the semiconductor region, a collector region of the second conductivity type selectively formed on a surface of the active layer, and a base contact region of the first conductivity type selectively formed on a surface of the active layer in separation from the emitter region and the collector region, respectively. When an inversion layer is formed at an interface between the insulation region and the active layer due to the voltage of the substrate, the semiconductor region suppresses an emitter current flowing via the inversion layer thereby allowing the emitter current to flow on the surface side of the active layer.

    摘要翻译： 半导体器件包括其表面由绝缘区域形成的衬底，形成在衬底上的第一导电类型的高电阻有源层，第一导电类型的第一半导体区域的杂质浓度高于 有源层，并且选择性地形成在有源层的表面上，选择性地形成在半导体区域的表面上的第二导电类型的发射极区域，选择性地形成在有源层的表面上的第二导电类型的集电极区域，以及 分别在与发射极区域和集电极区域分离的有源层的表面上分别形成有第一导电类型的基极接触区域。 当由于衬底的电压而在绝缘区域和有源层之间的界面处形成反型层时，半导体区域抑制通过反转层流动的发射极电流，从而允许发射极电流在 活动层

    Semiconductor device having FET structure with high breakdown voltage
    3.
    发明授权
    Semiconductor device having FET structure with high breakdown voltage 有权
    具有具有高击穿电压的FET结构的半导体器件

    公开(公告)号：US06380566B1

    公开(公告)日：2002-04-30

    申请号：US09669737

    申请日：2000-09-26

    申请人： Tomoko Matsudai ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Hirofumi Nagano ,  Akio Nakagawa

    发明人： Tomoko Matsudai ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Hirofumi Nagano ,  Akio Nakagawa

    IPC分类号： H01L2974

    CPC分类号： H01L29/7824 ,  H01L29/0847 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/78624

    摘要： An N-MOSFET is formed on an SOI substrate consisting of a semiconductor substrate, an insulating layer and an n−-active layer. A p-well layer, an n-RESURF layer, and an n-diffusion layer are formed in the surface of the n−-active layer between a source electrode and a drain electrode by means of impurity diffusion. The diffusion regions of the p-well layer and the n-RESURF layer overlap with each other. An end of the n-RESURF layer reaches a position below a gate electrode. The diffusion regions of the p-well layer and the n-diffusion layer do not overlap with each other, so that the n-RESURF layer has a region in direct contact with the n−-active layer between the p-well layer and the n-diffusion layer.

    摘要翻译： 在由半导体衬底，绝缘层和n-活性层组成的SOI衬底上形成N-MOSFET。 通过杂质扩散在源电极和漏电极之间的n-活性层的表面上形成p阱层，n-RESURF层和n扩散层。 p阱层和n-RESURF层的扩散区域彼此重叠。 n-RESURF层的一端到达栅电极下方的位置。 p阱层和n扩散层的扩散区域彼此不重叠，使得n-RESURF层具有与p阱层和p阱层之间的n-活性层直接接触的区域 n扩散层。

    Semiconductor device with horizontal MOSFET and Schottky barrier diode provided on single substrate
    6.
    发明授权
    Semiconductor device with horizontal MOSFET and Schottky barrier diode provided on single substrate 失效
    在单个基板上提供具有水平MOSFET和肖特基势垒二极管的半导体器件

    公开(公告)号：US07432579B2

    公开(公告)日：2008-10-07

    申请号：US10959201

    申请日：2004-10-07

    申请人： Tomoko Matsudai ,  Kazutoshi Nakamura ,  Akio Nakagawa

    发明人： Tomoko Matsudai ,  Kazutoshi Nakamura ,  Akio Nakagawa

    IPC分类号： H01L29/47 ,  H01L29/872

    CPC分类号： H01L27/0727

    摘要： A MOS field-effect transistor includes a semiconductor substrate of a first-conductivity type, a semiconductor layer of the first-conductivity type, a source region of a second-conductivity type, a first drain region of the second-conductivity type, a resurf layer of the second-conductivity type provided in the surface of the semiconductor layer between the source region and the first drain region in contact with the first drain region, and having a lower impurity concentration than the first drain region, a gate insulation film, and a gate electrode provided on the gate insulation film between the source region and resurf layer. A Schottky barrier diode includes a second drain region of the second-conductivity type provided in the surface of the semiconductor layer separate from the first drain region in a direction away from the gate electrode, and a Schottky electrode provided on the semiconductor layer between the first and second drain regions.

    摘要翻译： MOS场效应晶体管包括第一导电类型的半导体衬底，第一导电类型的半导体层，第二导电类型的源极区域，第二导电类型的第一漏极区域，第二导电类型的半导体层， 所述第二导电型层设置在与所述第一漏极区域接触的所述源极区域和所述第一漏极区域之间的所述半导体层的表面中，并且具有比所述第一漏极区域低的杂质浓度，栅极绝缘膜和 栅电极，设置在源极区域和复合层之间的栅极绝缘膜上。 肖特基势垒二极管包括设置在半导体层的表面上的第二导电类型的第二漏极区域，该第二漏极区域在远离栅极电极的方向上与第一漏极区域分开，以及肖特基电极，设置在第一 和第二漏区。

    Semiconductor device with horizontal MOSFET and schottky barrier diode provided on single substrate
    7.
    发明申请
    Semiconductor device with horizontal MOSFET and schottky barrier diode provided on single substrate 失效
    在单个衬底上提供具有水平MOSFET和肖特基势垒二极管的半导体器件

    公开(公告)号：US20050098845A1

    公开(公告)日：2005-05-12

    申请号：US10959201

    申请日：2004-10-07

    申请人： Tomoko Matsudai ,  Kazutoshi Nakamura ,  Akio Nakagawa

    发明人： Tomoko Matsudai ,  Kazutoshi Nakamura ,  Akio Nakagawa

    IPC分类号： H01L29/872 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/07 ,  H01L29/47 ,  H01L29/76

    CPC分类号： H01L27/0727

    摘要： A MOS field-effect transistor includes a semiconductor substrate of a first-conductivity type, a semiconductor layer of the first-conductivity type, a source region of a second-conductivity type, a first drain region of the second-conductivity type, a resurf layer of the second-conductivity type provided in the surface of the semiconductor layer between the source region and the first drain region in contact with the first drain region, and having a lower impurity concentration than the first drain region, a gate insulation film, and a gate electrode provided on the gate insulation film between the source region and resurf layer. A Schottky barrier diode includes a second drain region of the second-conductivity type provided in the surface of the semiconductor layer separate from the first drain region in a direction away from the gate electrode, and a Schottky electrode provided on the semiconductor layer between the first and second drain regions.

    摘要翻译： MOS场效应晶体管包括第一导电类型的半导体衬底，第一导电类型的半导体层，第二导电类型的源极区域，第二导电类型的第一漏极区域，第二导电类型的半导体层， 所述第二导电型层设置在与所述第一漏极区域接触的所述源极区域和所述第一漏极区域之间的所述半导体层的表面中，并且具有比所述第一漏极区域低的杂质浓度，栅极绝缘膜和 栅电极，设置在源极区域和复合层之间的栅极绝缘膜上。 肖特基势垒二极管包括设置在半导体层的表面上的第二导电类型的第二漏极区域，该第二漏极区域在远离栅极电极的方向上与第一漏极区域分开，以及肖特基电极，设置在第一 和第二漏区。

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20080251838A1

    公开(公告)日：2008-10-16

    申请号：US12118159

    申请日：2008-05-09

    申请人： Syotaro Ono ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Norio Yasuhara ,  Kenichi Matsushita ,  Shinichi Hodama ,  Akio Nakagawa

    发明人： Syotaro Ono ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Norio Yasuhara ,  Kenichi Matsushita ,  Shinichi Hodama ,  Akio Nakagawa

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7809

    摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.

    摘要翻译： 半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部 并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上， 以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。