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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5848011A

    公开(公告)日：1998-12-08

    申请号：US824737

    申请日：1997-03-26

    申请人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    发明人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  G11C11/401 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/065 ,  G11C7/12

    摘要： A semiconductor memory device including a memory cell array, bit lines, and sense amplifier groups. The memory cell array is composed of a plurality of memory cells arranged roughly in a matrix pattern. A plurality of the memory cells arranged in a row are activated in response to a row address decode signal. A pair of the bit lines are provided for each column. The data of the corresponding activated memory cells are transmitted to the bit line pair. Each of the sense amplifier groups has n-units of sense amplifiers each connected to the bit line pair, to sense and amplify data read to the bit line pair connected thereto. The respective reference potential terminals of the sense amplifiers of each of the sense amplifier groups are connected to a single common node which can be connected to a reference potential via a sense amplifier activating transistor turned on in response to a row address signal. The sense amplifiers can be operated at high speed, while preventing erroneous operation, because the wiring resistances and the parasitic capacitances of the common source node of the sense amplifiers can be reduced.

    摘要翻译： 一种包括存储单元阵列，位线和读出放大器组的半导体存储器件。 存储单元阵列由大致矩阵排列的多个存储单元构成。 响应于行地址解码信号，激活了排成行的多个存储单元。 为每列提供一对位线。 相应的激活的存储器单元的数据被发送到位线对。 读出放大器组中的每一个具有各自连接到位线对的读出放大器的n个单元，以检测和放大读取到与其连接的位线对的数据。 每个读出放大器组的读出放大器的各个参考电位端子连接到单个公共节点，该公共节点可以响应于行地址信号经由读出放大器激活晶体管导通而连接到参考电位。 由于读出放大器的公共源节点的布线电阻和寄生电容可以减小，所以读出放大器可以高速操作，同时防止错误的操作。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5640355A

    公开(公告)日：1997-06-17

    申请号：US471507

    申请日：1995-06-06

    申请人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    发明人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  G11C11/401 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/065 ,  G11C7/12

    摘要： A semiconductor memory device including a memory cell array, bit lines, and sense amplifier groups. The memory cell array is composed of a plurality of memory cells arranged roughly in a matrix pattern. A plurality of the memory cells arranged in a row are activated in response to a row address decode signal. A pair of the bit lines are provided for each column. The data of the corresponding activated memory cells are transmitted to the bit line pair. Each of the sense amplifier groups has n-units of sense amplifiers each connected to the bit line pair, to sense and amplify data read to the bit line pair connected thereto. The respective reference potential terminals of the sense amplifiers of each of the sense amplifier groups are connected to a single common node which can be connected to a reference potential via a sense amplifier activating transistor turned on in response to a row address signal. The sense amplifiers can be operated at high speed, while preventing erroneous operation, because the wiring resistances and the parasitic capacitances of the common source node of the sense amplifiers can be reduced.

    摘要翻译： 一种包括存储单元阵列，位线和读出放大器组的半导体存储器件。 存储单元阵列由大致矩阵排列的多个存储单元构成。 响应于行地址解码信号，激活了排成行的多个存储单元。 为每列提供一对位线。 相应的激活的存储器单元的数据被发送到位线对。 读出放大器组中的每一个具有各自连接到位线对的读出放大器的n个单元，以检测和放大读取到与其连接的位线对的数据。 每个读出放大器组的读出放大器的相应参考电位端子连接到单个公共节点，该公共节点可以响应于行地址信号经由读出放大器激活晶体管导通而连接到参考电位。 由于读出放大器的公共源节点的布线电阻和寄生电容可以减小，所以读出放大器可以高速操作，同时防止错误的操作。

    Semiconductor integrated circuit with sense amplifier control circuit
    4.
    发明授权
    Semiconductor integrated circuit with sense amplifier control circuit 失效
    半导体集成电路与读出放大器控制电路

    公开(公告)号：US5570047A

    公开(公告)日：1996-10-29

    申请号：US298837

    申请日：1994-08-31

    申请人： Eiichi Makino ,  Masaru Koyanagi ,  Kazuyoshi Muraoka

    发明人： Eiichi Makino ,  Masaru Koyanagi ,  Kazuyoshi Muraoka

    IPC分类号： G11C11/409 ,  G11C5/14 ,  H03K5/153 ,  G11C7/00

    CPC分类号： G11C5/147

    摘要： A semiconductor integrated circuit includes memory cell blocks having memory cells arranged in matrix, sense amplifiers, each located adjacent to the memory cells, and sense amplifier control circuits, each of the sense amplifier control circuit being located on outside of the memory cell block. The sense amplifier control circuit has a standard voltage generating circuit and a control circuit for receiving the standard voltage and for transferring a driver signal to the sense amplifier to control the charging ability of the sense amplifier. The source voltage has three voltage regions, first, intermediate, and second regions. In the first voltage region, the potential of the driver signal increases with the increase of the source voltage. In the intermediate voltage region (2.7 to 3 Volt), the potential of the driver signal is changed oppose to the change of the source voltage, and in the second voltage region, the potential of the driver signal decreases with the increase of the source voltage.

    摘要翻译： 半导体集成电路包括具有排列成矩阵的存储单元的存储单元块，每个位于与存储单元相邻的读出放大器，以及读出放大器控制电路，每个读出放大器控制电路位于存储单元块的外部。 读出放大器控制电路具有标准电压发生电路和用于接收标准电压并将驱动器信号传送到读出放大器以控制读出放大器的充电能力的控制电路。 源电压具有三个电压区域，第一，中间和第二区域。 在第一电压区域中，驱动信号的电位随源电压的增加而增加。 在中间电压区域（2.7〜3伏特）中，驱动信号的电位相对于源极电压的变化而变化，在第二电压区域中，驱动信号的电位随着源极电压的增加而减小 。

    Semiconductor device with supply voltage-lowering circuit
    6.
    发明授权
    Semiconductor device with supply voltage-lowering circuit 失效
    具有电源降压电路的半导体器件

    公开(公告)号：US5831421A

    公开(公告)日：1998-11-03

    申请号：US837461

    申请日：1997-04-18

    申请人： Takashi Taira ,  Kazuyoshi Muraoka

    发明人： Takashi Taira ,  Kazuyoshi Muraoka

    IPC分类号： H01L27/04 ,  G05F1/46 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  G05F3/16

    CPC分类号： G05F1/465

    摘要： A semiconductor device includes an internal circuit and first and second supply voltage-lowering circuits in its semiconductor chip. The first supply voltage-lowering circuit steps down an external power supply potential of the semiconductor chip in response to a control signal, generates a first internal power supply potential, and supplies it to the internal circuit. The second supply voltage-lowering circuit steps down the external power supply potential of the semiconductor chip in response to the control signal, generates a second internal power supply potential of substantially the same level as that of the first internal power supply potential, and supplies it to the internal circuit. The first and second internal power supply potentials output from the first and second supply voltage-lowering circuits vary out of phase with each other to cancel out variations in first and second internal power supply potentials.

    摘要翻译： 半导体器件包括其半导体芯片中的内部电路和第一和第二电源降压电路。 第一电源降压电路响应于控制信号降低半导体芯片的外部电源电位，产生第一内部电源电位，并将其提供给内部电路。 第二电源降压电路响应于控制信号降低半导体芯片的外部电源电位，产生与第一内部电源电位基本相同的第二内部电源电位，并将其提供 到内部电路。 从第一和第二电源电压降低电路输出的第一和第二内部电源电位彼此不同相异，以抵消第一和第二内部电源电位的变化。

    Semiconductor device including internal circuit having both states of active/precharge
    7.
    发明授权
    Semiconductor device including internal circuit having both states of active/precharge 失效
    半导体器件包括具有两种状态的有源/预充电的内部电路

    公开(公告)号：US5402010A

    公开(公告)日：1995-03-28

    申请号：US56408

    申请日：1993-05-04

    申请人： Kazuyoshi Muraoka

    发明人： Kazuyoshi Muraoka

    IPC分类号： G11C11/401 ,  G11C7/20 ,  G11C7/22 ,  G11C11/409 ,  G11C11/34

    CPC分类号： G11C7/20 ,  G11C7/22

    摘要： A semiconductor device has a plurality of internal circuits capable of having two conditions of an active state and a precharge state in the internal circuits. The device comprises signal generation element for generating a first signal which causes said internal circuits to be initialized until satisfying a predetermined condition from a time when the power is supplied; and state set element which is connected to an external apparatus through an interface which is supplied an external state signal, and for setting a precharge state of the internal circuits by outputting an internal state signal corresponding to the external state signal in response to a supply of the first signal from the signal generation element.

    摘要翻译： 半导体器件具有能够在内部电路中具有两种状态的激活状态和预充电状态的多个内部电路。 该装置包括用于产生第一信号的信号产生元件，该第一信号使得所述内部电路被初始化，直到从供电时起满足预定条件; 以及状态设定元件，其通过提供外部状态信号的接口连接到外部设备，并且用于通过输出与外部状态信号相对应的内部状态信号来设置内部电路的预充电状态， 来自信号发生元件的第一信号。

    Semiconductor memory having a spare memory cell
    8.
    发明申请
    Semiconductor memory having a spare memory cell 失效

    公开(公告)号：US20060146620A1

    公开(公告)日：2006-07-06

    申请号：US11363933

    申请日：2006-03-01

    申请人： Makoto Hamada ,  Kazuyoshi Muraoka ,  Masahiro Yoshihara

    发明人： Makoto Hamada ,  Kazuyoshi Muraoka ,  Masahiro Yoshihara

    IPC分类号： G11C29/00 ,  G11C17/18

    CPC分类号： G11C29/027 ,  G11C29/02

    摘要： A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.

    Semiconductor device having electric fuse element
    9.
    发明授权
    Semiconductor device having electric fuse element 失效
    具有电熔丝元件的半导体器件

    公开(公告)号：US06680873B2

    公开(公告)日：2004-01-20

    申请号：US10042937

    申请日：2002-01-08

    申请人： Kazuyoshi Muraoka ,  Eiji Kozuka

    发明人： Kazuyoshi Muraoka ,  Eiji Kozuka

    IPC分类号： G11C800

    CPC分类号： G11C29/785 ,  G11C17/16 ,  G11C17/18

    摘要： The output terminal of a voltage generation circuit is connected to one end portion of a fuse circuit. A transistor is connected to the other end portion of the fuse circuit. In program mode, a voltage generated from the voltage generation circuit is applied to the fuse circuit and a current flows through the fuse circuit and the transistor. In verify mode, a current generated from the voltage generation circuit flows into a pad through a selected fuse circuit and a detection circuit.

    摘要翻译： 电压产生电路的输出端连接到熔丝电路的一端。 晶体管连接到熔丝电路的另一端部。 在编程模式中，从电压产生电路产生的电压被施加到熔丝电路，并且电流流过熔丝电路和晶体管。 在验证模式下，从电压产生电路产生的电流通过选定的熔丝电路和检测电路流入焊盘。