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11 条记录 (耗时 0.014 秒)

    Microcomputer with synchronized data transfer
    1.
    发明授权
    Microcomputer with synchronized data transfer 失效
    微电脑同步数据传输

    公开(公告)号：US4975593A

    公开(公告)日：1990-12-04

    申请号：US255255

    申请日：1988-10-11

    申请人： Keiichi Kurakazu ,  Haruo Keida ,  Kazuyoshi Kikuta

    发明人： Keiichi Kurakazu ,  Haruo Keida ,  Kazuyoshi Kikuta

    IPC分类号： G06F13/38 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F15/78

    CPC分类号： G06F1/04 ,  G06F13/423

    摘要： A single-chip microcomputer has external terminals outputting a system clock signal, an address signal, and a data signals. External equipment such as an external memory is operated by address and signal which are output when the system clock signal changes. In the single-chip microcomputer of this invention, the operation of an address signal output circuit and that of a data signal output circuit are controlled by a signal output from a digital delay circuit which receives the system clock signal. According to this circuit construction, the hold time between the change in the system clock and the change in the address and data signals is determined by the delay circuit which exhibits a digital operation, so that the hold time can be set accurately without being affected adversely by any variation in the circuit elements due to the manufacturing process, or by temperature changes.

    摘要翻译： 单片机具有输出系统时钟信号，地址信号和数据信号的外部端子。 外部设备（如外部存储器）由系统时钟信号变化时输出的地址和信号进行操作。 在本发明的单片机中，地址信号输出电路和数据信号输出电路的动作由接收系统时钟信号的数字延迟电路输出的信号进行控制。 根据该电路结构，系统时钟的变化与地址和数据信号的变化之间的保持时间由展现数字操作的延迟电路确定，使得可以准确地设定保持时间而不受不利影响 由于制造过程中的电路元件的任何变化，或通过温度变化。

    Data processor in which external sync signal may be selectively inhibited
    3.
    发明授权
    Data processor in which external sync signal may be selectively inhibited 失效

    公开(公告)号：US5493686A

    公开(公告)日：1996-02-20

    申请号：US434292

    申请日：1995-05-03

    申请人： Haruo Keida ,  Takashi Tsukamoto ,  Nobutaka Nagasaki

    发明人： Haruo Keida ,  Takashi Tsukamoto ,  Nobutaka Nagasaki

    IPC分类号： G06F1/10 ,  G06F1/04 ,  G06F15/78

    CPC分类号： G06F1/10

    摘要： An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.

    Data processor in which external sync signal may be selectively inhibited
    4.
    发明授权
    Data processor in which external sync signal may be selectively inhibited 失效
    可以选择性地禁止外部同步信号的数据处理器

    公开(公告)号：US5179694A

    公开(公告)日：1993-01-12

    申请号：US577123

    申请日：1990-09-04

    申请人： Haruo Keida ,  Takashi Tsukamoto ,  Nobutaka Nagasaki

    发明人： Haruo Keida ,  Takashi Tsukamoto ,  Nobutaka Nagasaki

    IPC分类号： G06F1/10

    CPC分类号： G06F1/10

    摘要： An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.

    摘要翻译： 由单片机内的时钟发生电路产生的外部同步信号被提供给该芯片的外部端子。 外部同步信号在外部扩展模式下是必需的，但不是单芯片模式。 因此，通过控制栅极将外部同步信号提供给外部端子，同时将合适的控制信号输入到控制栅极的控制端子。 根据该电路结构，可以以这样的方式进行控制，使得外部同步信号不以单芯片模式提供给输出端子。 结果，可以通过单芯片模式中的外部端子之间的耦合容量来防止噪声进入相邻引脚的信号，并且降低输出缓冲电路的消耗功率，该输出缓冲电路设置在控制 门和外部端子。

    Data processor
    5.
    发明授权
    Data processor 失效
    数据处理器

    公开(公告)号：US4989208A

    公开(公告)日：1991-01-29

    申请号：US39695

    申请日：1987-04-20

    申请人： Yasushi Akao ,  Shinkichi Hotta ,  Haruo Keida

    发明人： Yasushi Akao ,  Shinkichi Hotta ,  Haruo Keida

    IPC分类号： G06F11/22 ,  G06F11/267 ,  G06F15/78

    CPC分类号： G06F11/2236 ,  G06F15/7814

    摘要： In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.

    摘要翻译： 在单片机中，形成诸如中央处理单元（CPU），用于存储程序的ROM，用于存储数据的RAM和用于输入和数据输出的I / O电路等功能块 在一个半导体衬底上。 地址数据用于选择CPU必须提供地址数据的内部总线中的功能块的预定区域。 缓冲电路能够从外部设备提供地址数据，并且被提供在微计算机中。 当功能块被测试时，地址数据直接从外部测试器提供给功能块，而不用CPU的指令执行，并且必要的数据从预定功能块的区域输出，通过缓冲电路，并且是 直接读取外部设备。 因此，提高了测试效率。

    Data processor in which external sync signal may be selectively inhibited
    6.
    发明授权
    Data processor in which external sync signal may be selectively inhibited 失效
    可以选择性地禁止外部同步信号的数据处理器

    公开(公告)号：US4967352A

    公开(公告)日：1990-10-30

    申请号：US230047

    申请日：1988-08-09

    申请人： Haruo Keida ,  Takashi Tsukamoto ,  Nobutaka Nagasaki

    发明人： Haruo Keida ,  Takashi Tsukamoto ,  Nobutaka Nagasaki

    IPC分类号： G06F15/78 ,  G06F1/10

    CPC分类号： G06F1/10

    摘要： An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.

    摘要翻译： 由单片机内的时钟发生电路产生的外部同步信号被提供给该芯片的外部端子。 外部同步信号在外部扩展模式下是必需的，但不是单芯片模式。 因此，通过控制栅极将外部同步信号提供给外部端子，同时将合适的控制信号输入到控制栅极的控制端子。 根据该电路结构，可以以这样的方式进行控制，使得外部同步信号不以单芯片模式提供给输出端子。 结果，可以通过单芯片模式中的外部端子之间的耦合容量来防止噪声进入提供给相邻引脚的信号，并且降低输出缓冲电路的消耗功率，该输出缓冲电路被布置在控制 门和外部端子。

    MISFET switching circuit for a high withstand voltage
    7.
    发明授权
    MISFET switching circuit for a high withstand voltage 失效
    用于高耐压的MISFET开关电路

    公开(公告)号：US3991326A

    公开(公告)日：1976-11-09

    申请号：US634189

    申请日：1975-11-21

    申请人： Hiroto Kawagoe ,  Haruo Keida

    发明人： Hiroto Kawagoe ,  Haruo Keida

    IPC分类号： G09G3/04 ,  H01L27/088 ,  H03K17/10 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0944 ,  H03K19/08 ,  H03K19/40 ,  H05B39/00

    CPC分类号： H03K17/102 ,  G09G3/04 ,  H01L27/0883 ,  H03K19/00315 ,  H03K19/09443

    摘要： A switching circuit for use as, e.g., a digitron driver circuit in an electronic desk top calculator, comprises a driving MISFET whose source terminal is connected to a ground reference potential, at least one protective MISFET whose source terminal is connected to a drain terminal of the driving MISFET, and a bias power source which is connected through a load to a drain terminal of the protective MISFET. A d.c. voltage is applied to a gate terminal of the protective MISFET and an output signal is derived from the drain terminal of the protective MISFET on the basis of an input signal which is supplied to a gate terminal of the driving MISFET. The driving MISFET is an enhancement mode transistor, while the protective MISFET is a depletion mode transistor, whereby the withstand voltage of the switching circuit is enhanced.

    摘要翻译： 用作电子桌面计算器中的数字驱动电路的开关电路包括其源极端子连接到接地参考电位的驱动MISFET，至少一个保护MISFET，其源极端子连接到漏极端子 驱动MISFET和通过负载连接到保护MISFET的漏极端子的偏置电源。 一个d.c. 电压施加到保护MISFET的栅极端子，并且基于提供给驱动MISFET的栅极端子的输入信号从保护MISFET的漏极端子导出输出信号。 驱动MISFET是增强型晶体管，而保护MISFET是耗尽型晶体管，由此提高了开关电路的耐受电压。

    Data processor in which external sync signal may be selectively inhibited
    9.
    发明授权
    Data processor in which external sync signal may be selectively inhibited 失效

    公开(公告)号：US5497482A

    公开(公告)日：1996-03-05

    申请号：US301740

    申请日：1994-09-07

    申请人： Haruo Keida ,  Takashi Tsukamoto ,  Nobutaka Nagasaki

    发明人： Haruo Keida ,  Takashi Tsukamoto ,  Nobutaka Nagasaki

    IPC分类号： G06F1/10 ,  G06F13/00 ,  G06F1/04

    CPC分类号： G06F1/10

    摘要： An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.

    Data processor
    10.
    发明授权
    Data processor 失效
    数据处理器

    公开(公告)号：US5247521A

    公开(公告)日：1993-09-21

    申请号：US848547

    申请日：1992-03-09

    申请人： Yasushi Akao ,  Shinkichi Hotta ,  Haruo Keida

    发明人： Yasushi Akao ,  Shinkichi Hotta ,  Haruo Keida

    IPC分类号： G06F11/267 ,  G06F15/78

    CPC分类号： G06F11/2236 ,  G06F15/7814

    摘要： In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.

    摘要翻译： 在单片机中，形成诸如中央处理单元（CPU），用于存储程序的ROM，用于存储数据的RAM和用于输入和数据输出的I / O电路等功能块 在一个半导体衬底上。 地址数据用于选择CPU必须提供地址数据的内部总线中的功能块的预定区域。 缓冲电路能够从外部设备提供地址数据，并且被提供在微计算机中。 当功能块被测试时，地址数据直接从外部测试器提供给功能块，而不用CPU的指令执行，并且必要的数据从预定功能块的区域输出，通过缓冲电路，并且是 直接读取外部设备。 因此，提高了测试效率。