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    Semiconductor device and fabrication method therefor
    1.
    发明申请
    Semiconductor device and fabrication method therefor 有权
    半导体器件及其制造方法

    公开(公告)号：US20060278936A1

    公开(公告)日：2006-12-14

    申请号：US11444216

    申请日：2006-05-30

    申请人： Kenichi Fujii ,  Masahiko Higashi

    发明人： Kenichi Fujii ,  Masahiko Higashi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/26513 ,  H01L21/74 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

    摘要： There are provided a semiconductor device and a fabrication method therefor including an ONO film (18) formed on a semiconductor substrate (10), a word line (24) formed on the ONO film (18), a bit line (20) formed in the semiconductor substrate (10), and a conductive layer (32) that is in contact with the bit line (20), runs in a length direction of the bit line (20), and includes a polysilicon layer or a metal layer. In accordance with the present invention, a semiconductor device and a fabrication method therefor are provided wherein degradation of the writing and erasing characteristics and degradation of the transistor characteristics such as a junction leakage are suppressed, and the bit line resistance is decreased.

    摘要翻译： 提供了一种半导体器件及其制造方法，其包括形成在半导体衬底（10）上的ONO膜（18），形成在ONO膜（18）上的字线（24），形成在 半导体衬底（10）和与位线（20）接触的导电层（32）在位线（20）的长度方向上延伸，并且包括多晶硅层或金属层。 根据本发明，提供一种半导体器件及其制造方法，其中抑制了写入和擦除特性的劣化以及诸如结漏电的晶体管特性的劣化，并且位线电阻降低。

    Fabrication method for semiconductor device having laminated electronic conductor on bit line
    2.
    发明授权
    Fabrication method for semiconductor device having laminated electronic conductor on bit line 有权
    在位线上具有层叠电子导体的半导体器件的制造方法

    公开(公告)号：US08278171B2

    公开(公告)日：2012-10-02

    申请号：US13081777

    申请日：2011-04-07

    申请人： Kenichi Fujii ,  Masahiko Higashi

    发明人： Kenichi Fujii ,  Masahiko Higashi

    IPC分类号： H01L21/336

    CPC分类号： H01L21/26513 ,  H01L21/74 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

    摘要： There are provided a semiconductor device and a fabrication method therefor including an ONO film (18) formed on a semiconductor substrate (10), a word line (24) formed on the ONO film (18), a bit line (20) formed in the semiconductor substrate (10), and a conductive layer (32) that is in contact with the bit line (20), runs in a length direction of the bit line (20), and includes a polysilicon layer or a metal layer. In accordance with the present invention, a semiconductor device and a fabrication method therefor are provided wherein degradation of the writing and erasing characteristics and degradation of the transistor characteristics such as a junction leakage are suppressed, and the bit line resistance is decreased.

    摘要翻译： 提供了一种半导体器件及其制造方法，其包括形成在半导体衬底（10）上的ONO膜（18），形成在ONO膜（18）上的字线（24），形成在 半导体衬底（10）和与位线（20）接触的导电层（32）在位线（20）的长度方向上延伸，并且包括多晶硅层或金属层。 根据本发明，提供一种半导体器件及其制造方法，其中抑制了写入和擦除特性的劣化以及诸如结漏电的晶体管特性的劣化，并且位线电阻降低。

    Semiconductor device having laminated electronic conductor on bit line
    3.
    发明授权
    Semiconductor device having laminated electronic conductor on bit line 有权
    半导体器件在位线上具有层叠电子导体

    公开(公告)号：US07943982B2

    公开(公告)日：2011-05-17

    申请号：US11444216

    申请日：2006-05-30

    申请人： Kenichi Fujii ,  Masahiko Higashi

    发明人： Kenichi Fujii ,  Masahiko Higashi

    IPC分类号： H01L29/792

    CPC分类号： H01L21/26513 ,  H01L21/74 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

    摘要： There are provided a semiconductor device and a fabrication method therefor including an ONO film (18) formed on a semiconductor substrate (10), a word line (24) formed on the ONO film (18), a bit line (20) formed in the semiconductor substrate (10), and a conductive layer (32) that is in contact with the bit line (20), runs in a length direction of the bit line (20), and includes a polysilicon layer or a metal layer. In accordance with the present invention, a semiconductor device and a fabrication method therefor are provided wherein degradation of the writing and erasing characteristics and degradation of the transistor characteristics such as a junction leakage are suppressed, and the bit line resistance is decreased.

    摘要翻译： 提供了一种半导体器件及其制造方法，其包括形成在半导体衬底（10）上的ONO膜（18），形成在ONO膜（18）上的字线（24），形成在 半导体衬底（10）和与位线（20）接触的导电层（32）在位线（20）的长度方向上延伸，并且包括多晶硅层或金属层。 根据本发明，提供一种半导体器件及其制造方法，其中抑制了写入和擦除特性的劣化以及诸如结漏电的晶体管特性的劣化，并且位线电阻降低。

    PROTECTION DIODE AND SEMICONDUCTOR DEVICE HAVING THE SAME
    7.
    发明申请
    PROTECTION DIODE AND SEMICONDUCTOR DEVICE HAVING THE SAME 审中-公开
    保护二极管和具有该保护二极管的半导体器件

    公开(公告)号：US20130020673A1

    公开(公告)日：2013-01-24

    申请号：US13547496

    申请日：2012-07-12

    申请人： Atsushi HIRAMA ,  Masahiko Higashi

    发明人： Atsushi HIRAMA ,  Masahiko Higashi

    IPC分类号： H01L27/08

    CPC分类号： H01L27/0255 ,  H01L29/0649 ,  H01L29/861

    摘要： A protection diode includes a semiconductor substrate having a first region, a second region surrounding the first region, and a third region surrounding the second region; a first insulation layer disposed between the second region and the third region; a first conductive type semiconductor portion disposed in the third region; a second conductive type semiconductor portion disposed in the second region; and a capacity reduction layer disposed in the first region.

    摘要翻译： 保护二极管包括具有第一区域，围绕第一区域的第二区域和围绕第二区域的第三区域的半导体衬底; 设置在所述第二区域和所述第三区域之间的第一绝缘层; 设置在所述第三区域中的第一导电型半导体部分; 设置在所述第二区域中的第二导电型半导体部分; 以及设置在所述第一区域中的容量降低层。

    HEAT-RESISTANT ALLOY MEMBER, ALLOY MEMBER FOR FUEL CELL, COLLECTOR MEMBER FOR FUEL CELL, CELL STACK, AND FUEL CELL APPARATUS
    8.
    发明申请
    HEAT-RESISTANT ALLOY MEMBER, ALLOY MEMBER FOR FUEL CELL, COLLECTOR MEMBER FOR FUEL CELL, CELL STACK, AND FUEL CELL APPARATUS 审中-公开
    耐热合金会员，燃料电池用合金会员，燃料电池收集器部件，电池组和燃料电池装置

    公开(公告)号：US20090297917A1

    公开(公告)日：2009-12-03

    申请号：US12091734

    申请日：2006-10-27

    申请人： Masahiko Higashi ,  Tetsuro Fujimoto

    发明人： Masahiko Higashi ,  Tetsuro Fujimoto

    IPC分类号： H01M8/02 ,  B32B15/04 ,  H01M2/02

    CPC分类号： H01M8/021 ,  H01M8/0204 ,  H01M8/0208 ,  H01M8/0217 ,  H01M8/0228 ,  H01M8/2425

    摘要： The present invention provides a heat-resistant alloy member which hardly causes external diffusion of Cr, an alloy member for a fuel cell, a collector member for a fuel cell, a cell stack, and a fuel cell apparatus.The surface of a collector base material 201 containing Cr is coated with a Cr diffusion preventing layer 203 made of an oxide containing Zn and Mn and a coating layer 202 made of an oxide containing Zn is formed on the surface of the Cr diffusion preventing layer 203. The coating layer 202 preferably contains at least one kind of Al and Fe as a trivalent or higher valent positive metal element.

    摘要翻译： 本发明提供一种难以引起Cr的外部扩散的耐热合金构件，燃料电池用合金构件，燃料电池用集电体构件，电池组以及燃料电池装置。 包含Cr的集电体基材201的表面涂覆有由包含Zn和Mn的氧化物制成的Cr扩散防止层203，并且在Cr扩散防止层203的表面上形成由包含Zn的氧化物制成的涂层202 涂层202优选含有三价以上的金属元素中的至少一种Al和Fe。

    Semiconductor device and method of fabrication
    10.
    发明申请
    Semiconductor device and method of fabrication 有权
    半导体器件及其制造方法

    公开(公告)号：US20060076598A1

    公开(公告)日：2006-04-13

    申请号：US11237591

    申请日：2005-09-27

    申请人： Masahiko Higashi ,  Hiroyuki Nansei

    发明人： Masahiko Higashi ,  Hiroyuki Nansei

    IPC分类号： H01L29/94

    CPC分类号： H01L27/105 ,  H01L21/26586 ,  H01L27/11534 ,  H01L27/11568

    摘要： A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si3N4.

    摘要翻译： 半导体存储器件采用SONOS型存储器架构，并且在其中埋入导电膜的浅沟槽沟槽中包括位线扩散层。 这使得可以在不扩大半导体衬底的主表面上的面积的情况下降低位线扩散层的电阻率，并且制造具有稳定的电特性的半导体存储器件而不扩大单元面积。 位线通过将离子注入到Si 3 N 4 N 3的侧壁中而形成。