公开(公告)号：US20120056145A1

公开(公告)日：2012-03-08

申请号：US13018765

申请日：2011-02-01

申请人： Kenji AOYAMA ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

发明人： Kenji AOYAMA ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

IPC分类号： H01L45/00 ,  H01L21/02 ,  B82Y40/00 ,  B82Y30/00

CPC分类号： H01L45/16 ,  B82Y10/00 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/149 ,  H01L45/1608 ,  H01L45/1675

摘要： According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.

摘要翻译： 根据一个实施例，非易失性存储器件包括选择元件层和纳米材料聚集层。 选择元件层包括硅。 纳米材料聚集层层叠在选择元件层上。 纳米材料聚集体层包括分散在微导电体之间的多个间隙中的多个微导电体和微粒。 至少微细颗粒的表面由氧化硅以外的绝缘材料制成。

公开(公告)号：US20120217464A1

公开(公告)日：2012-08-30

申请号：US13404678

申请日：2012-02-24

申请人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

发明人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

IPC分类号： H01L45/00

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/149

摘要： A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.

摘要翻译： 通过层叠多个存储单元阵列形成非易失性存储装置，所述存储单元阵列包括多个字线，多个位线和存储单元。 存储单元包括电流整流装置和可变电阻装置，可变电阻装置包括下电极，上电极和包括形成在下电极和上电极之间的导电纳米材料的电阻变化层， 在层叠方向上彼此相邻设置的可变电阻装置在电阻变化层和作为阴极的下部电极之间具有钛氧化物（TiOx），另外在层叠方向上彼此相邻设置的可变电阻装置具有钛 电阻变化层和作为阴极的上部电极之间的氧化物（TiOx）。

公开(公告)号：US08895952B2

公开(公告)日：2014-11-25

申请号：US13404678

申请日：2012-02-24

申请人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

发明人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/149

摘要： A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.

摘要翻译： 通过层叠多个存储单元阵列形成非易失性存储装置，所述存储单元阵列包括多个字线，多个位线和存储单元。 存储单元包括电流整流装置和可变电阻装置，可变电阻装置包括下电极，上电极和包括形成在下电极和上电极之间的导电纳米材料的电阻变化层， 在层叠方向上彼此相邻设置的可变电阻装置在电阻变化层和作为阴极的下部电极之间具有钛氧化物（TiOx），另外在层叠方向上彼此相邻设置的可变电阻装置具有钛 电阻变化层和作为阴极的上部电极之间的氧化物（TiOx）。

公开(公告)号：US08507888B2

公开(公告)日：2013-08-13

申请号：US13018765

申请日：2011-02-01

申请人： Kenji Aoyama ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

发明人： Kenji Aoyama ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

IPC分类号： H01L45/00

CPC分类号： H01L45/16 ,  B82Y10/00 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/149 ,  H01L45/1608 ,  H01L45/1675

摘要： According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.

摘要翻译： 根据一个实施例，非易失性存储器件包括选择元件层和纳米材料聚集层。 选择元件层包括硅。 纳米材料聚集层层叠在选择元件层上。 纳米材料聚集体层包括分散在微导电体之间的多个间隙中的多个微导电体和微粒。 至少微细颗粒的表面由氧化硅以外的绝缘材料制成。

公开(公告)号：US20120104352A1

公开(公告)日：2012-05-03

申请号：US13052426

申请日：2011-03-21

申请人： Kenji AOYAMA ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

发明人： Kenji AOYAMA ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

IPC分类号： H01L45/00 ,  H01L21/62 ,  B82Y10/00 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L45/1675 ,  B82Y10/00 ,  B82Y40/00 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149

摘要： According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.

摘要翻译： 根据一个实施例，存储器件包括纳米材料组装层，第一电极层和第二电极层。 纳米材料组装层通过微导体之间的间隙由多个微导体的组件形成。 第一电极层设置在纳米材料组装层上。 第二电极层设置在第一电极层上。

公开(公告)号：US08686384B2

公开(公告)日：2014-04-01

申请号：US13052426

申请日：2011-03-21

申请人： Kenji A{dot over (o)}yama ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

发明人： Kenji A{dot over (o)}yama ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

IPC分类号： H01L21/00

CPC分类号： H01L45/1675 ,  B82Y10/00 ,  B82Y40/00 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149

摘要： According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.

摘要翻译： 根据一个实施例，存储器件包括纳米材料组装层，第一电极层和第二电极层。 纳米材料组装层通过微导体之间的间隙由多个微导体的组件形成。 第一电极层设置在纳米材料组装层上。 第二电极层设置在第一电极层上。

公开(公告)号：US08716691B2

公开(公告)日：2014-05-06

申请号：US12973183

申请日：2010-12-20

申请人： Shigeto Oshino

发明人： Shigeto Oshino

IPC分类号： H01L45/00

CPC分类号： B82Y10/00 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/149 ,  H01L45/16

摘要： According to one embodiment, a nonvolatile memory device includes a lower electrode layer, a nanomaterial assembly layer, and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of micro conductive bodies assembled via a gap. The upper electrode layer is provided on the nanomaterial assembly layer. The portion of the micro conductive bodies is buried at least in a lower part of the upper electrode layer.

摘要翻译： 根据一个实施例，非易失性存储器件包括下电极层，纳米材料组件层和上电极层。 纳米材料组装层设置在下电极层上，并且包括经由间隙组装的多个微导电体。 上电极层设置在纳米材料组装层上。 至少在上电极层的下部埋设微导电体的一部分。