公开(公告)号：US08212112B2

公开(公告)日：2012-07-03

申请号：US12676473

申请日：2008-09-05

申请人： Kenji Fujino ,  Hiroshi Sekiguchi

发明人： Kenji Fujino ,  Hiroshi Sekiguchi

IPC分类号： A01H5/00 ,  A01H5/10 ,  C12N15/29 ,  C12N15/63

CPC分类号： C07K14/415 ,  C12N15/8273

摘要： The present invention provides a gene participating in the low temperature germinability in rice and utilization of the same, and the invention relates to a gene for a low temperature germinability which is an isolated qLTG-3-1 gene from the rice line Italica Livorno, has low temperature germinability and has the base sequence of SEQ ID NO: 1; an amino acid sequence encoded by the gene; a transgenic plant transformed with the gene for the low temperature germinability to improve the low temperature germinability; a method of analyzing low temperature germinability, including analyzing the low temperature germinability of a cultivar by comparing the base sequence of the gene for the low temperature germinability with the genotype of the cultivar; a method of improving the low temperature germinability of rice, including transforming the gene for the low temperature germinability into a rice cultivar to improve the low temperature germinability of the cultivar under low temperature conditions; and a method of analyzing the low temperature germinability of a rice cultivar by utilizing the expression of the gene for the low temperature germinability.

摘要翻译： 本发明提供参与水稻低温发芽性的基因及其利用，本发明涉及一种低温发芽性基因，该基因是水稻品系Italica Livorno中分离的qLTG-3-1基因，具有 具有低温发芽性，并具有SEQ ID NO：1的碱基序列; 由该基因编码的氨基酸序列; 转基因植物转基因为低温发芽性，提高低温发芽率; 分析低温发芽率的方法，包括通过比较低温发芽能力基因的碱基序列与品种的基因型来分析品种的低温发芽率; 提高水稻低温发芽率的方法，包括将低温发芽基因转化为水稻品种，以提高低温条件下品种的低温发芽率; 以及通过利用该基因表达低温发芽性来分析水稻品种的低温发芽率的方法。

公开(公告)号：US07369160B2

公开(公告)日：2008-05-06

申请号：US10170500

申请日：2002-06-14

申请人： Kenji Fujino ,  Tooru Katsurai ,  Shuuji Yamamoto ,  Hisanori Hayashi ,  Ryoutatsu Iga ,  Gentarou Fukano ,  Harumi Wada

发明人： Kenji Fujino ,  Tooru Katsurai ,  Shuuji Yamamoto ,  Hisanori Hayashi ,  Ryoutatsu Iga ,  Gentarou Fukano ,  Harumi Wada

IPC分类号： H04N5/232

CPC分类号： H04N5/23206 ,  H04N5/232 ,  H04N5/235 ,  H04N7/18

摘要： An object of the present invention is to realize a camera system suitable for remote monitoring. The present invention is made by making improvements to a camera system that transmits camera image data to a network. The camera system includes a camera head including an image sensor and a sensor controller that controls the image sensor; a video signal processing means that performs video signal processing on image data from the image sensor; and a web server which transmits image data from the video signal processing means as the camera image data to the network, receives control data from the network, and controls at least the sensor controller or the video signal processing means.

摘要翻译： 本发明的目的是实现适合于远程监控的摄像机系统。 本发明是通过改进将相机图像数据传送到网络的相机系统进行的。 相机系统包括摄像头，包括图像传感器和控制图像传感器的传感器控制器; 对来自图像传感器的图像数据执行视频信号处理的视频信号处理装置; 以及将来自视频信号处理装置的图像数据作为摄像机图像数据发送到网络的网络服务器，从网络接收控制数据，并且至少控制传感器控制器或视频信号处理装置。

公开(公告)号：US20060254955A1

公开(公告)日：2006-11-16

申请号：US10491060

申请日：2002-09-30

申请人： Takashi Kaimai ,  Yoshiyuki Morishima ,  Kenji Fujino

发明人： Takashi Kaimai ,  Yoshiyuki Morishima ,  Kenji Fujino

IPC分类号： C10M101/02 ,  C10M177/00

CPC分类号： C10M101/02 ,  C08K5/01 ,  C10G21/00 ,  C10G53/16 ,  C10G67/0418 ,  C10G2300/1074 ,  C10G2300/1077 ,  C10G2300/301 ,  C10G2300/302 ,  C10G2300/44 ,  C10M2203/1006 ,  C10M2203/1085 ,  C10N2220/02 ,  C10N2220/022 ,  C10N2220/026 ,  C10N2220/031 ,  C10N2230/02 ,  C10N2230/64 ,  C08L21/00

摘要： A process oil comprising a 95/5 to 5/95 by weight mixture of: an extract having a DMSO extractable content less than 3 wt % obtained by solvent-extracting an oil obtained by deasphalting a vacuum distillation bottom; and either a mineral oil base having a DMSO extractable content less than 3 wt % which is a raffinate obtained by the solvent refining of a vacuum distillate or a mineral oil base having a DMSO extractable content less than 3 wt % obtained by subjecting a raffinate obtained by the solvent refining of a vacuum distillate to hydrorefining and/or dewaxing. The process oil has a kinematic viscosity at lOOoC of less than 32 mm2/s, % CA of 15 to 30, aniline point of lOOoC or lower, weight change through evaporation of 0.5% or less, and mutagenicity index of less than 1.

摘要翻译： 一种加工油，其包含95/5至5/95重量比的混合物，其通过溶剂萃取通过脱气真空蒸馏塔得到的油获得的DMSO可提取物含量小于3wt％的提取物; 以及DMSO萃取物含量小于3重量％的矿物油基料，其是通过真空馏出物的溶剂精制获得的萃余液或具有小于3重量％的DMSO可提取物含量的矿物油基料，所述提取物含量通过使获得的萃余液 通过真空馏出物的溶剂精制进行加氢精制和/或脱蜡。 工艺油在100℃下的运动粘度小于32mm 2 / s，％CA为15〜30，苯胺点为100℃以下，蒸发重量变化为0.5％以下，致突变性指数小于1。

公开(公告)号：US5134578A

公开(公告)日：1992-07-28

申请号：US685340

申请日：1991-04-15

申请人： Steven L. Garverick ,  Kenji Fujino

发明人： Steven L. Garverick ,  Kenji Fujino

IPC分类号： G01R19/00 ,  G01R21/00 ,  G01R21/133 ,  G05B19/042 ,  G06F7/544 ,  G06F15/78 ,  G06F17/10

CPC分类号： G06F15/7842 ,  G05B19/0423 ,  G06F7/5443 ,  G06F7/5446 ,  G01R21/006 ,  G05B2219/25254

摘要： A bit-serial processor for selectively carrying out the sequential steps of performing by successive approximations Coordinate Rotation Digital Computation (CORDIC), non-restoring division or non-restoring square rooting calculations is suitable for inclusion in a monolithic integrated circuit with a plurality of sensors for generating respective sensor output signals, circuitry for converting each sensor output signal to bit-serial digital format, and a bit-serial muliptly-add processor. Together with an electrically-erasable programmable read-only memory and a plurality of current transformers, the monolithic integrated circuit implements a system for metering a-c power main conductors.

摘要翻译： 用于选择性地执行通过逐次逼近执行的顺序步骤的位串行处理器坐标旋转数字计算（CORDIC），非恢复分割或非恢复平方根生根计算适用于包含在具有多个传感器的单片集成电路 用于产生相应的传感器输出信号，用于将每个传感器输出信号转换为比特串行数字格式的电路和一个位串行多媒体加法处理器。 与电可擦除可编程只读存储器和多个电流互感器一起，单片集成电路实现用于计量a-c电源主导体的系统。

公开(公告)号：US6078137A

公开(公告)日：2000-06-20

申请号：US955750

申请日：1997-10-22

申请人： Kazuhiko Tojo ,  Tatsuya Yoshino ,  Hiroto Komatsu ,  Kenji Fujino

发明人： Kazuhiko Tojo ,  Tatsuya Yoshino ,  Hiroto Komatsu ,  Kenji Fujino

IPC分类号： G09F9/30 ,  H01J29/92 ,  H05K3/32 ,  H01J63/04 ,  H01J5/50

CPC分类号： H01J31/126 ,  H01J29/92 ,  H01J2329/92 ,  H05K3/325

摘要： A display panel which can reduce the number of external terminals for a fluorescent display tube and has its simplified assembled structure difficult to cause conduction failure. The base substrate of the container for a fluorescent display tube protrudes partially outward. Conductors electrically connected to the electrodes inside the container are derived out from the container to electrically connect to the external electrodes on the substrate. Connection terminals are formed on the substrate. The conductive rubber connector includes a non-conductive portion 39 with a nearly L-shaped cross section in which plural conductive fine wires bent in a nearly U-shaped form are buried at predetermined intervals. The fluorescent display tube is mounted on the upper surface of the printed board. The conductive rubber connector is placed at a predetermined position. The fluorescent display tube and the conductive rubber connector are fixed by means of a fixture. The external terminals of the fluorescent display tube is electrically connected to the connection terminals of the printed board via the conductive rubber connector.

摘要翻译： 可以减少荧光显示管的外部端子数量并且其组装结构简单难以导致导通故障的显示面板。 用于荧光显示管的容器的基底部分向外突出。 与容器内的电极电连接的导体从容器中导出，以电连接到基板上的外部电极。 连接端子形成在基板上。 导电橡胶连接器包括具有大致L形横截面的非导电部分39，其中以预定间隔掩埋以几乎U形的形式弯曲的多个导电细线。 荧光显示管安装在印刷电路板的上表面上。 导电橡胶连接器放置在预定位置。 荧光显示管和导电橡胶连接器通过固定装置固定。 荧光显示管的外部端子通过导电橡胶连接器电连接到印刷电路板的连接端子。

公开(公告)号：US5349676A

公开(公告)日：1994-09-20

申请号：US653935

申请日：1991-02-11

申请人： Steven L. Garverick ,  Kenji Fujino

发明人： Steven L. Garverick ,  Kenji Fujino

IPC分类号： G01R19/00 ,  G01R21/00 ,  G01R21/133 ,  G05B19/042 ,  G06F7/544 ,  G06F15/78 ,  G06F17/10 ,  G06F7/68 ,  G06F7/70 ,  G06F9/302

CPC分类号： G06F15/7842 ,  G05B19/0423 ,  G06F7/5443 ,  G06F7/5446 ,  G01R21/006 ,  G05B2219/25254

摘要： A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.

摘要翻译： 可以与用于产生各个传感器输出信号的多个传感器组合使用的单片集成电路，该单片集成电路包括用于将每个传感器输出信号转换为位串行数字格式的装置，以及一些初始处理电路，包括一位 - 系列乘法加法处理器。 该处理器包括位串行数字乘法器，用于将位串行形式的第一数字处理器输入信号乘以第二数字处理器输入信号以产生数字乘积信号;数字加法器，用于将第三数字处理器输入信号加到数字 产生信号以产生数字和信号，以及用于向数字处理器输出信号提供与所述数字和信号相对应的位的装置。 存储器系统提供用于存储程序指令的存储器，用于存储第二数字处理器输入信号的连续值的存储器，用于存储第三数字处理器输入信号的连续值的存储器和用于存储数字处理器输出信号的连续值的存储器， 进入内存系统。 可以从传感器输出信号中选择第一个数字处理器输入信号，转换为位串行数字格式。 应用于位串行乘法加法处理器的第二数字处理器输入信号至少在从存储器系统读取的选定时间，以及施加到位串行乘法加法处理器的第三数字处理器输入信号。 控制器从用于存储程序指令的存储器中以规定的顺序检索存储的程序指令，并且生成用于至少控制存储器系统的读取和写入以及第一数字处理器输入信号的选择的控制信号。

公开(公告)号：US4536712A

公开(公告)日：1985-08-20

申请号：US528599

申请日：1983-09-01

申请人： Hideto Iwaoka ,  Kenji Fujino ,  Tadashi Sugiyama ,  Hiroyuki Matsuura

发明人： Hideto Iwaoka ,  Kenji Fujino ,  Tadashi Sugiyama ,  Hiroyuki Matsuura

IPC分类号： A61B10/00 ,  A61B5/055 ,  G01R33/48 ,  G01R33/54 ,  G01R33/08

CPC分类号： G01R33/482

摘要： An examination method and apparatus utilizes a nuclear magnetic resonance technique in which the body of a subject to be examined is placed in a uniform static magnetic field and subjected to an electromagnetic wave having a frequency which induces nuclear magnetic resonance, a magnetic field is also applied to the subject body to specify an area of the body from which nuclear magnetic resonance (NMR) signals are radiated, and such nuclear magnetic resonance signals from the specified body area are received. A first 90.degree. pulse as the electromagnetic wave is applied to the body to excite the same, and then a 180.degree. pulse is applied to the body to produce an echo signal. A second 90.degree. pulse is to the body when the echo signal is maximum to thereby allow a magnetization to return to a state of thermal equilibrium. The foregoing sequence of the steps is repeated at prescribed intervals.

摘要翻译： 一种检查方法和装置利用核磁共振技术，其中待检查对象的身体被置于均匀的静磁场中并且经受具有诱发核磁共振的频率的电磁波，也施加磁场 指定主体以指定辐射核磁共振（NMR）信号的身体的区域，并且接收来自指定身体区域的这种核磁共振信号。 将第一个90度脉冲作为电磁波施加到身体上以激发它，然后将180度脉冲施加到身体以产生回波信号。 当回波信号最大时，第二个90度脉冲是指身体，从而允许磁化返回到热平衡状态。 以规定的间隔重复上述步骤顺序。

公开(公告)号：US07851088B2

公开(公告)日：2010-12-14

申请号：US10806206

申请日：2004-03-23

申请人： Takeshi Takahashi ,  Takeshi Oba ,  Kenji Fujino ,  Junichi Tokuno ,  Masuhiro Morizaki ,  Takeyuki Kondo ,  Jun Seyama

发明人： Takeshi Takahashi ,  Takeshi Oba ,  Kenji Fujino ,  Junichi Tokuno ,  Masuhiro Morizaki ,  Takeyuki Kondo ,  Jun Seyama

IPC分类号： H01M4/48 ,  H01M4/52 ,  H01M4/58 ,  C01G51/04 ,  C01G53/04

CPC分类号： H01M4/131 ,  H01M4/366 ,  H01M4/485 ,  H01M4/505 ,  H01M4/525 ,  H01M10/0431 ,  H01M10/0525 ,  H01M10/0587

摘要： Disclosed is a positive electrode active material for a nonaqueous electrolyte secondary battery having at least a lithium-transition metal composite oxide of a layer structure, in which an existence ratio of at least one selected from the group consisting of elements which may become tetravalent and magnesium is 20% or more on a surface of the lithium-transition metal composite oxide. By use of this positive electrode active material, a nonaqueous electrolyte secondary battery having excellent battery characteristics, specifically, having excellent high rate characteristics, cycle characteristics, low-temperature characteristics, thermal stability, and the like, under the even more harsh environment for use can be realized.

摘要翻译： 公开了一种非水电解质二次电池用正极活性物质，其至少具有层状结构的锂 - 过渡金属复合氧化物，其中选自可能成为四价的元素和镁中的至少一种的存在比例与镁 在锂 - 过渡金属复合氧化物的表面上为20％以上。 通过使用该正极活性物质，在更恶劣的环境下使用具有优异的电池特性的非水电解质二次电池，具体地，具有优异的高速率特性，循环特性，低温特性，热稳定性等 可以实现。

公开(公告)号：US07601253B2

公开(公告)日：2009-10-13

申请号：US10491060

申请日：2002-09-30

申请人： Takashi Kaimai ,  Yoshiyuki Morishima ,  Kenji Fujino

发明人： Takashi Kaimai ,  Yoshiyuki Morishima ,  Kenji Fujino

IPC分类号： C07C7/10 ,  C10M101/02

CPC分类号： C10M101/02 ,  C08K5/01 ,  C10G21/00 ,  C10G53/16 ,  C10G67/0418 ,  C10G2300/1074 ,  C10G2300/1077 ,  C10G2300/301 ,  C10G2300/302 ,  C10G2300/44 ,  C10M2203/1006 ,  C10M2203/1085 ,  C10N2220/02 ,  C10N2220/022 ,  C10N2220/026 ,  C10N2220/031 ,  C10N2230/02 ,  C10N2230/64 ,  C08L21/00

摘要： A process oil comprising a 95/5 to 5/95 by weight mixture of: an extract having a DMSO extractable content less than 3 wt % obtained by solvent-extracting an oil obtained by deasphalting a vacuum distillation bottom; and either a mineral oil base having a DMSO extractable content less than 3 wt % which is a raffinate obtained by the solvent refining of a vacuum distillate or a mineral oil base having a DMSO extractable content less than 3 wt % obtained by subjecting a raffinate obtained by the solvent refining of a vacuum distillate to hydrorefining and/or dewaxing. The process oil has a kinematic viscosity at 100° C. of less than 32 mm2/s, % CA of 15 to 30, aniline point of 100° C. or lower, weight change through evaporation of 0.5% or less, and mutagenicity index of less than 1.

摘要翻译： 一种加工油，其包含95/5至5/95重量比的混合物，其通过溶剂萃取通过脱气真空蒸馏塔得到的油获得的DMSO可提取物含量小于3wt％的提取物; 以及DMSO萃取物含量小于3重量％的矿物油基料，其是通过真空馏出物的溶剂精制获得的萃余液或具有小于3重量％的DMSO可提取物含量的矿物油基料，所述提取物含量通过使获得的萃余液 通过真空馏出物的溶剂精制进行加氢精制和/或脱蜡。 工艺油在100℃下的运动粘度小于32mm 2 / s，％CA为15〜30，苯胺点为100℃以下，蒸发重量变化为0.5％以下，诱变性指数 小于1。

公开(公告)号：US5448747A

公开(公告)日：1995-09-05

申请号：US250122

申请日：1994-05-27

申请人： Steven L. Garverick ,  Kenji Fujino

发明人： Steven L. Garverick ,  Kenji Fujino

IPC分类号： G01R19/00 ,  G01R21/00 ,  G01R21/133 ,  G05B19/042 ,  G06F7/544 ,  G06F15/78 ,  G06F17/10 ,  G06F7/38

CPC分类号： G06F15/7842 ,  G05B19/0423 ,  G06F7/5443 ,  G06F7/5446 ,  G01R21/006 ,  G05B2219/25254

摘要： A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.

摘要翻译： 可以与用于产生各个传感器输出信号的多个传感器组合使用的单片集成电路，该单片集成电路包括用于将每个传感器输出信号转换为位串行数字格式的装置，以及一些初始处理电路，包括一位 - 系列乘法加法处理器。 该处理器包括位串行数字乘法器，用于将位串行形式的第一数字处理器输入信号乘以第二数字处理器输入信号以产生数字乘积信号;数字加法器，用于将第三数字处理器输入信号加到数字 产生信号以产生数字和信号，以及用于向数字处理器输出信号提供与所述数字和信号相对应的位的装置。 存储器系统提供用于存储程序指令的存储器，用于存储第二数字处理器输入信号的连续值的存储器，用于存储第三数字处理器输入信号的连续值的存储器和用于存储数字处理器输出信号的连续值的存储器， 进入内存系统。 可以从传感器输出信号中选择第一个数字处理器输入信号，转换为位串行数字格式。 应用于位串行乘法加法处理器的第二数字处理器输入信号至少在从存储器系统读取的选定时间，以及施加到位串行乘法加法处理器的第三数字处理器输入信号。 控制器从用于存储程序指令的存储器中以规定的顺序检索存储的程序指令，并且生成用于至少控制存储器系统的读取和写入以及第一数字处理器输入信号的选择的控制信号。