公开(公告)号：US4543499A

公开(公告)日：1985-09-24

申请号：US366784

申请日：1982-04-08

申请人： Kenji Kaneko ,  Minoru Nagata ,  Makoto Furihata ,  Setsuo Ogura ,  Takahiro Okabe ,  Mitsuya Sato

发明人： Kenji Kaneko ,  Minoru Nagata ,  Makoto Furihata ,  Setsuo Ogura ,  Takahiro Okabe ,  Mitsuya Sato

IPC分类号： H01L21/8226 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H03K19/091 ,  H03K19/092

CPC分类号： H01L27/0244 ,  H01L27/06

摘要： A semiconductor integrated circuit includes low voltage operation circuitries such as I.sup.2 L and high voltage operation circuitries operating at a higher voltage than the low voltage operation circuitries. Both of the low and high voltage operation circuitries are implemented in a single semiconductor chip in coexistence with each other. The low voltage operation circuitries are disposed in constant current paths in the high voltage operation circuitries so that the currents once used by the high voltage operation circuits are utilized again by the low voltage operation circuitries. Power dissipation of the whole integrated circuit is thus reduced significantly.

摘要翻译： 半导体集成电路包括低电压操作电路，例如I2L和高电压工作电路，工作电压高于低电压工作电路。 低电压和高电压操作电路都可以在单个半导体芯片中实现，彼此共存。 低电压工作电路在高电压工作电路中以恒定电流通路设置，使得高电压操作电路一度使用的电流被低压操作电路再利用。 因此整个集成电路的功耗显着降低。

公开(公告)号：US4697102A

公开(公告)日：1987-09-29

申请号：US737872

申请日：1985-05-28

申请人： Takahiro Okabe ,  Makoto Hayashi ,  Katuhiro Morisuye ,  Tomoyuki Watanabe ,  Katsuyoshi Washio ,  Setsuo Ogura ,  Makoto Furihata ,  Shizuo Kondo

发明人： Takahiro Okabe ,  Makoto Hayashi ,  Katuhiro Morisuye ,  Tomoyuki Watanabe ,  Katsuyoshi Washio ,  Setsuo Ogura ,  Makoto Furihata ,  Shizuo Kondo

IPC分类号： H03K19/00 ,  H03K19/013 ,  H03K19/082

CPC分类号： H03K19/001 ,  H03K19/013

摘要： A logic circuit is provided which includes a first multi-emitter transistor with its emitters coupled to a group of first input lines and a first transistor with its base coupled to the collector of said first multi-emitter transistor. A second transistor is also provided with its base coupled to the collector of said first transistor, said second transistor having a polarity opposite to that of said first multi-emitter transistor. A second multi-emitter transistor is connected with its base coupled to the collector of said second transistor and with its emitters coupled to a group of second input lines, and a third transistor is connected with its base coupled to the collector of said second multi-emitter transistor and with its collector coupled to an output line. The collector of said first multi-emitter transistor is coupled to the emitter of said second multi-emitter transistor in order to absorb minority carriers stored in the transistors. This feature significantly improves the circuit operating speed. A further feature is the provision of a logic circuit which is highly integrated and which consumes reduced amounts of electric power, while maintaining high-speed performance of the TTL circuit, by substituting a multi-collector transistor that reversely operates for an inverter portion of the TTL circuit.

摘要翻译： 提供了一种逻辑电路，其包括第一多发射极晶体管，其发射极耦合到一组第一输入线，第一晶体管的基极耦合到所述第一多发射极晶体管的集电极。 第二晶体管还设置有其基极耦合到所述第一晶体管的集电极，所述第二晶体管具有与所述第一多发射极晶体管的极性相反的极性。 第二多发射极晶体管与其基极耦合，耦合到所述第二晶体管的集电极，并且其发射极耦合到一组第二输入线，并且第三晶体管与其基极连接，耦合到所述第二多晶体管的集电极， 发射极晶体管，其集电极耦合到输出线。 所述第一多发射极晶体管的集电极耦合到所述第二多发射极晶体管的发射极，以便吸收存储在晶体管中的少数载流子。 该功能显着提高了电路工作速度。 另一个特征是提供了一种高度集成的逻辑电路，并且通过将反向工作的多集电极晶体管替换为逆变器部分的多集电极晶体管，同时维持TTL电路的高速性能，从而消耗了较少的电功率 TTL电路。

公开(公告)号：US5132806A

公开(公告)日：1992-07-21

申请号：US538448

申请日：1990-06-15

申请人： Yukinori Kitamura ,  Setsuo Ogura ,  Shiro Mayuzumi ,  Shunji Mori ,  Toshiyuki Fukamachi ,  Yuji Kobayashi ,  Kouichi Yamazaki ,  Makoto Furihata ,  Kazuyuki Kamegaki

发明人： Yukinori Kitamura ,  Setsuo Ogura ,  Shiro Mayuzumi ,  Shunji Mori ,  Toshiyuki Fukamachi ,  Yuji Kobayashi ,  Kouichi Yamazaki ,  Makoto Furihata ,  Kazuyuki Kamegaki

IPC分类号： H01L21/761 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/082 ,  H04N9/79

CPC分类号： H04N9/79 ,  H01L27/0207 ,  H01L2224/05554 ,  H01L2224/45147 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/1301 ,  H01L2924/1305 ,  Y10S257/906

摘要： Disclosed is a novel semiconductor integrated circuit device for use in a color VTR (Video Tape Recorder). Concretely, the semiconductor integrated circuit device comprises a substantially rectangular semiconductor chip which has a principal surface, a luminance signal processing unit and a color signal processing unit which are disposed at the positions of the principal surface opposing to each other, and a semiconductor region which is provided in the interspace of the principal surface between the luminance signal and color signal processing units opposing to each other and which is supplied with a bias stable A.C.-wise. Further, the semiconductor region is located substantially at the central portion of the semiconductor chip and is extended so as to intersect with one set of opposing sides of the rectangular semiconductor chip.

摘要翻译： 公开了一种用于彩色VTR（录像机）的新型半导体集成电路装置。 具体地，半导体集成电路器件包括：主体表面的基本上矩形的半导体芯片，设置在彼此相对的主表面的位置处的亮度信号处理单元和颜色信号处理单元;以及半导体区域， 设置在彼此相对的亮度信号和颜色信号处理单元之间的主表面的间隙中，并且被提供有偏置稳定的交流方式。 此外，半导体区域基本上位于半导体芯片的中心部分并且被延伸以与矩形半导体芯片的一组相对侧相交。

公开(公告)号：US4725745A

公开(公告)日：1988-02-16

申请号：US643260

申请日：1984-08-22

申请人： Shizuo Kondo ,  Setsuo Ogura ,  Eiji Minamimura ,  Makoto Furihata

发明人： Shizuo Kondo ,  Setsuo Ogura ,  Eiji Minamimura ,  Makoto Furihata

IPC分类号： H01L27/112 ,  H03K19/0944 ,  H03K19/177 ,  H03K19/02 ,  G06F7/38 ,  H03K19/091

CPC分类号： H03K19/09448 ,  H01L27/112 ,  H03K19/17708

摘要： An integrated programmable logic array formed within a single silicon chip comprises a combination of a logical product gate array and a logical summation gate array. The logical product gate array is equipped with a plurality of MIS field-effect transistors whose gates are selectively driven by a plurality of input signals. Source-drain paths of these transistors are connected in series. The logical summation gate array is equipped with a plurality of inverted bipolar transistors having collector-emitter paths which are connected in parallel.

摘要翻译： 形成在单个硅芯片内的集成可编程逻辑阵列包括逻辑乘积门阵列和逻辑求和门阵列的组合。 逻辑积门阵列配备有多个MIS场效应晶体管，其栅极由多个输入信号选择性地驱动。 这些晶体管的源极 - 漏极路径串联连接。 逻辑求和门阵列配备有多个并联连接的集电极 - 发射极路径的反向双极晶体管。

公开(公告)号：US4659947A

公开(公告)日：1987-04-21

申请号：US665385

申请日：1984-10-26

申请人： Setsuo Ogura ,  Shizuo Kondo ,  Eiji Minamimura ,  Makoto Furihata

发明人： Setsuo Ogura ,  Shizuo Kondo ,  Eiji Minamimura ,  Makoto Furihata

IPC分类号： H03K19/091 ,  H03K19/177 ,  H03K19/082

CPC分类号： H03K19/17708

摘要： An integrated programmable logic array formed within a single silicon chip comprises a combination of an NAND or AND gate array and an NOR or OR gate array.The NAND or AND gate array includes a plurality of bipolar transistors which are driven to operate in the forward direction by a plurality of input signals, and a plurality of Schottky barrier diodes provided between the collectors of the bipolar transistors and output signal lines. The NOR or OR gate array includes a plurality of other bipolar transistors which are driven to operate in the backward direction by a plurality of output signals from the NAND or AND gate array.

摘要翻译： 形成在单个硅芯片内的集成可编程逻辑阵列包括NAND或与门阵列和NOR或OR门阵列的组合。 NAND或与门阵列包括多个双极晶体管，其被驱动以通过多个输入信号在正向工作，以及设置在双极晶体管的集电极和输出信号线之间的多个肖特基势垒二极管。 NOR或OR门阵列包括多个其它双极晶体管，其被驱动以通过来自NAND或与门阵列的多个输出信号在向后方向上工作。

公开(公告)号：US4670859A

公开(公告)日：1987-06-02

申请号：US704412

申请日：1985-02-22

申请人： Makoto Furihata ,  Setsuo Ogura ,  Shizuo Kondo ,  Eiji Minamimura

发明人： Makoto Furihata ,  Setsuo Ogura ,  Shizuo Kondo ,  Eiji Minamimura

IPC分类号： G11C17/00 ,  H03K19/00 ,  H03K19/091

CPC分类号： H03K19/091 ,  H03K19/001

摘要： A logic circuit of a large scale which consumes small amounts of electric power is comprised of a plurality of ROM portions each formed of IIL circuits. Input signal lines are commonly used to transmit input signals to the ROM portions. The plurality of ROM portions are selectively operated by ROM select signals, and outputs corresponding to the input signals are obtained from a selected ROM portion. To select a particular ROM portion out of the plurality of ROM portions, the emitters of inverse npn transistors of IIL circuits constituting the selected ROM portion are rendered to assume ground potential. In the meantime, the emitters of the inverse npn transistors of IIL circuits in the non-selected ROM portions are held in a floating condition. This makes it possible to obtain a logic circuit which consumes small amounts of electric power with a very simple construction since the non-selected ROM portions consume no power.

摘要翻译： 消耗少量电力的大规模的逻辑电路包括由IIL电路形成的多个ROM部分。 输入信号线通常用于将输入信号发送到ROM部分。 多个ROM部分由ROM选择信号选择性地操作，并且从所选择的ROM部分获得对应于输入信号的输出。 为了选择多个ROM部分中的特定ROM部分，构成所选择的ROM部分的IIL电路的逆npn晶体管的发射极被呈现为地电位。 同时，未选择的ROM部分中的IIL电路的逆npn晶体管的发射极保持在浮置状态。 这使得可以以非常简单的结构获得消耗少量电力的逻辑电路，因为未选择的ROM部分不消耗电力。

公开(公告)号：US3961360A

公开(公告)日：1976-06-01

申请号：US504364

申请日：1974-09-09

申请人： Mitsuya Sato ,  Yozo Tanihara ,  Makoto Furihata

发明人： Mitsuya Sato ,  Yozo Tanihara ,  Makoto Furihata

IPC分类号： H03D3/18 ,  H04N9/66 ,  H04N9/68 ,  H04N9/50 ,  H03D13/00

CPC分类号： H04N9/66

摘要： In a synchronizing detector circuit which has at least two differential transistors, a pair of constant current transistors are connected to the differential transistors, and an output transistor is connected to the junctures between the differential and constant current transistors and to a filter circuit for detection. A synchronizing detector circuit comprises a compensating circuit incorporated between the junctures and the filter circuit and includes a constant current absorbing circuit, so as to prevent an offset output voltage of the filter circuit due to noise.

摘要翻译： 在具有至少两个差分晶体管的同步检测器电路中，一对恒流晶体管连接到差分晶体管，并且输出晶体管连接到差分和恒流晶体管之间的接合点，并连接到用于检测的滤波电路。 一个同步检测器电路包括一个结合在接点和滤波器电路之间的补偿电路，并包括一个恒定电流吸收电路，以便防止由于噪声引起的滤波器电路的偏移输出电压。

公开(公告)号：US5526126A

公开(公告)日：1996-06-11

申请号：US258953

申请日：1994-06-13

申请人： Makoto Furihata ,  Takashi Jin ,  Kenya Yamauchi ,  Shinichi Ishihara ,  Kouichi Yamazaki

发明人： Makoto Furihata ,  Takashi Jin ,  Kenya Yamauchi ,  Shinichi Ishihara ,  Kouichi Yamazaki

IPC分类号： H04N9/80 ,  H04N9/793 ,  H04N9/83 ,  H04N9/84 ,  H04N9/79

CPC分类号： H04N9/83 ,  H04N9/793 ,  H04N9/84

摘要： A first reproduced color under signal is delayed by one or two horizontal periods by a delay circuit, and this delayed second reproduced color under signal and the aforementioned first reproduced color under signal have their frequencies converted individually by first and second frequency converters into standard color signals. An oscillatory frequency signals of 2n of carriers for the aforementioned frequency conversions are divided to have the aforementioned carrier frequencies and to produce four carriers having phases of 0, 90, 180 and 270 degrees. These carriers are selectively fed to the first and second frequency converters by switches so that the two frequency-converted signals are subtracted or added in phase or in opposite phase to clear the noise (or crosstalk component), which is caused by the crosstalk between the tracks.

摘要翻译： 信号下的第一再现颜色由延迟电路延迟一个或两个水平周期，并且信号下的延迟的第二再现颜色和信号下的上述第一再现颜色的频率由第一和第二变频器分别转换为标准色彩信号 。 用于上述频率转换的2n个载波的振荡频率信号被划分为具有上述载波频率并且产生具有0,90,180和270度相位的四个载波。 这些载波通过开关选择性地馈送到第一和第二变频器，使得两个频率转换的信号被相位相减或相位相加以清除噪声（或串扰分量），这是由于 轨道

公开(公告)号：US4368354A

公开(公告)日：1983-01-11

申请号：US112815

申请日：1980-01-17

申请人： Makoto Furihata ,  Masanori Oguino ,  Noboru Sakata

发明人： Makoto Furihata ,  Masanori Oguino ,  Noboru Sakata

IPC分类号： H04N5/60 ,  H04H1/00 ,  H04H40/36 ,  H04N7/06 ,  H04H5/00 ,  H04N7/00

CPC分类号： H04H40/36 ,  H04N7/06

摘要： A discriminator apparatus for a television multivoice system comprises a mixer for mixing a program identifying signal with a reference signal thereby to produce a differential beat signal. A reference signal generator includes a signal source of an original frequency, and a frequency converter for converting the original frequency to the reference frequency which is close to the frequency of the program identifying signal and so selected that the frequency of the differential beat signal is lower than the lowest audible frequency. A low-pass filter is employed for extracting the differential beat signal. Need for expensive mechanical filters of a narrow fractional bandwidth is thereby eliminated.

摘要翻译： 一种用于电视多频发音系统的鉴别器装置，包括用于将节目识别信号与参考信号混合从而产生差分拍频信号的混合器。 参考信号发生器包括原始频率的信号源，以及用于将原始频率转换为接近节目识别信号频率的参考频率并被选择为差分差拍信号的频率较低的频率转换器 比最低的可听频率。 采用低通滤波器来提取差分拍频信号。 因此消除了对狭窄分数带宽的昂贵机械滤波器的需求。

公开(公告)号：US5351089A

公开(公告)日：1994-09-27

申请号：US13376

申请日：1993-02-04

申请人： Yoshiyuki Matsumoto ,  Makoto Furihata

发明人： Yoshiyuki Matsumoto ,  Makoto Furihata

IPC分类号： H04N9/64 ,  H04N9/45 ,  H04N9/66

CPC分类号： H04N9/641

摘要： A video signal processing device comprises: a unit for extracting a first color burst signal from a first video signal; a unit for generating a first subcarrier in synchronism with the first color burst signal extracted from the first video signal; a unit for extracting a second chrominance signal and a second color burst signal from a second video signal; a unit for demodulating the second chrominance signal and the second color burst signal on the basis of the first subcarrier to obtain a demodulated second color signal and a demodulated second color burst signal; and an operating unit for performing operation process of the demodulated second color signal on the basis of the demodulated second color burst signal in a manner such that the demodulated second color signal is converted into a corrected color signal which is substantially the same as an imaginal second color signal which is obtained on the assumption that the second chrominance signal is demodulated on the basis of a second subcarrier synchronized with the second color burst signal extracted from the second video signal.

摘要翻译： 视频信号处理装置包括：用于从第一视频信号中提取第一色同步信号的单元; 用于与从第一视频信号提取的第一色同步信号同步地产生第一子载波的单元; 用于从第二视频信号中提取第二色度信号和第二色同步信号的单元; 基于所述第一子载波来解调所述第二色度信号和所述第二色同步信号的单元，以获得解调的第二颜色信号和解调的第二色同步信号; 以及操作单元，用于以解调的第二颜色信号被转换为与想象的第二颜色信号基本相同的校正颜色信号的方式，基于解调的第二色同步信号来执行解调的第二颜色信号的操作处理 基于与从第二视频信号提取的第二色同步信号同步的第二副载波来解调第二色度信号而获得的彩色信号。