公开(公告)号：US5305272A

公开(公告)日：1994-04-19

申请号：US111738

申请日：1993-08-25

申请人： Kenji Matsuo ,  Yasukazu Noine ,  Kazuhiko Kasai ,  Yoshihiro Kato ,  Kazuaki Umetsu

发明人： Kenji Matsuo ,  Yasukazu Noine ,  Kazuhiko Kasai ,  Yoshihiro Kato ,  Kazuaki Umetsu

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C7/1048 ,  G11C11/419 ,  G11C7/062

摘要： In a sense amplifier circuit, an output potential is set in a data output state when an operation of the sense amplifier is a worst pass before the start of read access. In a memory read mode, when data corresponding to the worst-pass operation of the sense amplifier circuit is read out, the circuit is previously set in a corresponding data output state. A time delay (gate delay) by a gate does not occur. In contrast, when data corresponding to the best-pass operation of the sense amplifier circuit is read out, the gate delay occurs by this operation. The gate delay, however, is shorter than that of the worst pass. As a result, only the best pass is present as the operation mode of the sense amplifier circuit. Therefore, a high operation speed is achieved, so that a high read speed of the entire memory is achieved.

摘要翻译： 在读出放大器电路中，当在读取访问开始之前读出放大器的操作是最差通过时，输出电位被设置在数据输出状态。 在存储器读取模式中，当读出对应于读出放大器电路的最差通过操作的数据时，电路被预先设置为相应的数据输出状态。 不会发生门的延时（门延迟）。 相反，当读出对应于读出放大器电路的最佳通过操作的数据时，通过该操作发生门延迟。 然而，门延迟比最差通过时更短。 结果，仅存在最佳通过作为读出放大器电路的操作模式。 因此，实现了高的运行速度，从而实现了整个存储器的高读取速度。

公开(公告)号：US5136293A

公开(公告)日：1992-08-04

申请号：US710119

申请日：1991-06-04

申请人： Kenji Matsuo ,  Yasukazu Noine ,  Kazuhiko Kasai

发明人： Kenji Matsuo ,  Yasukazu Noine ,  Kazuhiko Kasai

IPC分类号： H03M1/74 ,  H03K17/687 ,  H03M1/08

CPC分类号： H03M1/0845 ,  H03M1/742

摘要： This invention is a D/A converter including a preset current source, first and second differential switches for selectively deriving an output current of the preset current source in response to complementary signals supplied to control electrodes thereof, and an imaginary short circuit for connecting output portions of current paths of the switches to each other. Variation in the voltage at the time of switching operation of the differential switch can be suppressed by use of the imaginary short circuit with the above construction, thus making it possible to enhance the operation speed.

公开(公告)号：US5200637A

公开(公告)日：1993-04-06

申请号：US658461

申请日：1991-02-22

申请人： Kenji Matsuo ,  Yasukazu Noine ,  Kazuhiko Kasai

发明人： Kenji Matsuo ,  Yasukazu Noine ,  Kazuhiko Kasai

IPC分类号： H01L29/423

CPC分类号： H01L29/4238

摘要： A MOS transistor includes a gate electrode layer formed on an insulation layer which is formed on an element formation region defined by a field insulation layer formed on a P-type semiconductor substrate. The gate electrode layer has first and second openings formed therein. Further, N-type impurity diffusion regions acting as the drain and source of the MOS transistor are formed in those portions of the surface area of the semiconductor substrate which lie under the first and second openings.

摘要翻译： MOS晶体管包括形成在绝缘层上的栅极电极层，该绝缘层形成在由形成在P型半导体衬底上的场绝缘层限定的元件形成区域上。 栅电极层具有形成在其中的第一和第二开口。 此外，在位于第一和第二开口下方的半导体衬底的表面区域的那些部分中形成用作MOS晶体管的漏极和源极的N型杂质扩散区域。

公开(公告)号：US5235218A

公开(公告)日：1993-08-10

申请号：US791379

申请日：1991-11-14

申请人： Kenji Matsuo ,  Shinji Fujii ,  Yasukazu Noine ,  Kazuhiko Kasai

发明人： Kenji Matsuo ,  Shinji Fujii ,  Yasukazu Noine ,  Kazuhiko Kasai

IPC分类号： H03M1/74 ,  H03K17/041 ,  H03K17/687 ,  H03K17/693 ,  H03M1/76

CPC分类号： H03K17/04106 ,  H03K17/693

摘要： This invention discloses a switching constant current source circuit including a first current path for supplying a constant current, a first MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a second current path, and a gate of which is applied with a digital signal corresponding to a logical amplitude, a second MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a third current path, and which performs a switching operation complementary with the first MOS transistor, and level conversion means for fetching a change in voltage in the first current path caused by a change in current flowing through the first current path according to an operation of the first MOS transistor in response to the digital signal, and alternately applying a first level for disabling the second MOS transistor, which operates complementarily with the first MOS transistor, and a second level for enabling the second MOS transistor to output a predetermined current.

公开(公告)号：US5406135A

公开(公告)日：1995-04-11

申请号：US156627

申请日：1993-11-24

申请人： Kazuhiko Kasai ,  Kenji Matsuo ,  Shinji Fujii ,  Yasukazu Noine

发明人： Kazuhiko Kasai ,  Kenji Matsuo ,  Shinji Fujii ,  Yasukazu Noine

IPC分类号： G05F3/24 ,  H03F3/45 ,  H03K17/041 ,  H03K17/693 ,  H03M1/74 ,  H03M3/02 ,  H03F3/16

CPC分类号： H03K17/04106 ,  H03K17/693

摘要： A differential current source circuit includes three P-channel MOSFETs and two N-channel MOSFETs. Each source of first and second P-channel MOSFETs is connected to a power supply, and a bias voltage is applied to each gate of the MOSFETs. A current path of the first N-channel MOSFET is connected between a drain of the first P-channel MOSFET and a ground. A current path of the third P-channel MOSFET is connected between a drain of the second P-channel MOSFET and a current output terminal. A gate of the third P-channel MOSFET is connected to the drain of the first P-channel MOSFET. One end of a current path of the second N-channel MOSFET is connected to a connecting point of the first P-channel and first N-channel MOSFETs, and the other end is connected to a connecting point of the second P-channel and third P-channel MOSFETs. A digital signal is applied to a gate of the second N-channel MOSFET.

摘要翻译： 差分电流源电路包括三个P沟道MOSFET和两个N沟道MOSFET。 第一和第二P沟道MOSFET的每个源连接到电源，并且偏置电压施加到MOSFET的每个栅极。 第一N沟道MOSFET的电流路径连接在第一P沟道MOSFET的漏极和地之间。 第三P沟道MOSFET的电流路径连接在第二P沟道MOSFET的漏极和电流输出端子之间。 第三P沟道MOSFET的栅极连接到第一P沟道MOSFET的漏极。 第二N沟道MOSFET的电流路径的一端连接到第一P沟道和第一N沟道MOSFET的连接点，另一端连接到第二P沟道和第三N沟道MOSFET的连接点 P沟道MOSFET。 数字信号被施加到第二N沟道MOSFET的栅极。

公开(公告)号：US20080246750A1

公开(公告)日：2008-10-09

申请号：US12057469

申请日：2008-03-28

申请人： Kenji Shino ,  Yasukazu Noine

发明人： Kenji Shino ,  Yasukazu Noine

IPC分类号： G06F3/038

CPC分类号： G09G3/22 ,  G09G2300/06 ,  G09G2310/0205 ,  G09G2310/0267 ,  G09G2320/0223

摘要： There is provided a driving circuit including; a plurality of output terminals to be electrically connected to the scan wirings, respectively; a scan controlling unit for selecting one or plural output terminals to output a driving signal for the scan wiring from among the plurality of output terminals; a potential correcting unit for controlling a potential of the driving signal on the basis of a difference voltage between the potential of the selected output terminal and a reference potential; and a reference potential adjusting unit for adjusting the reference potential in response to a current passing through the selected output terminal in order to correct a voltage drop caused by a member connected to the selected output terminal. The reference potential adjusting unit changes adjustment of the reference potential in response to the number of the selected output terminals.

摘要翻译： 提供一种驱动电路，包括： 多个输出端子分别电连接到扫描布线; 扫描控制单元，用于选择一个或多个输出端子，以从多个输出端子中输出用于扫描布线的驱动信号; 电位校正单元，用于根据所选择的输出端子的电位与参考电位之间的差电压来控制驱动信号的电位; 以及参考电位调整单元，用于响应于通过所选择的输出端子的电流来调整参考电位，以便校正由连接到所选择的输出端子的构件引起的电压降。 参考电位调整单元响应于所选择的输出端子的数量来改变参考电位的调整。

公开(公告)号：US20060250345A1

公开(公告)日：2006-11-09

申请号：US11406443

申请日：2006-04-19

申请人： Kenji Shino ,  Yasukazu Noine

发明人： Kenji Shino ,  Yasukazu Noine

IPC分类号： G09G3/36

CPC分类号： G09G3/22 ,  G09G2300/06 ,  G09G2310/0267 ,  G09G2320/0209 ,  G09G2320/0223

摘要： A scanning circuit having a plurality of output units each outputs an ON potential sequentially, comprises: a first output unit that changes an ON potential to an OFF potential during a first period; and a second output unit that changes the OFF potential to the ON potential during a second period, wherein at least part of the first period and at least part of the second period overlap.

摘要翻译： 具有多个输出单元的扫描电路各自依次输出ON电位，包括：第一输出单元，其在第一周期期间将ON电位改变为OFF电位; 以及第二输出单元，其在第二时段期间将所述OFF电位改变为ON电位，其中所述第一周期的至少一部分和所述第二周期的至少部分重叠。

公开(公告)号：US20090195522A1

公开(公告)日：2009-08-06

申请号：US12362882

申请日：2009-01-30

申请人： Kenji Shino ,  Yasukazu Noine

发明人： Kenji Shino ,  Yasukazu Noine

IPC分类号： G09G5/00

CPC分类号： G09G3/22 ,  G09G3/2014 ,  G09G2300/0465 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/025 ,  G09G2330/028 ,  H03K17/167

摘要： A drive circuit for driving a display panel having wirings and display devices to be connected to the wirings, has a first switch that transits potential of the wirings toward the first potential, a feedback amplifier that maintains the potentials of the wirings at the first potential, and a second switch that selects whether or not to supply an output from the feedback amplifier to the wirings. The first switch and the second switch are connected to the wirings in parallel. A drive performance of the first switch is lower than that of the feedback amplifier. As a result, stable driving waveforms can be output in a simple and inexpensive circuit configuration.

摘要翻译： 用于驱动具有布线的显示面板和要连接到布线的显示装置的驱动电路具有使配线的电位朝向第一电位的第一开关，将布线的电位维持在第一电位的反馈放大器， 以及第二开关，其选择是否将来自反馈放大器的输出提供给布线。 第一开关和第二开关并联连接到布线。 第一开关的驱动性能低于反馈放大器的驱动性能。 结果，可以以简单且廉价的电路配置输出稳定的驱动波形。

公开(公告)号：US5767697A

公开(公告)日：1998-06-16

申请号：US584487

申请日：1996-01-11

申请人： Masaji Ueno ,  Yasukazu Noine

发明人： Masaji Ueno ,  Yasukazu Noine

IPC分类号： H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/094

CPC分类号： H03K19/00315 ,  H03K19/018521

摘要： A low-voltage output circuit has the first and the second MOS transistors. An input signal is fed to the gate of the first transistor. Either of the source and the drain of the first transistor is supplied with a predetermined potential. The other is connected to an output terminal and generates an output signal. The first transistor raises the output signal to the predetermined potential level in response to the input signal. Either of the source and the drain of the second MOS transistor is connected to the gate of the first transistor. The other is connected to the output terminal. The circuit further includes a device for supplying a bias voltage to a gate of the second transistor so that the first and second transistors remain turned off at different gate bias potentials and the second transistor turns on before the first transistor when the output signal is raised to the predetermined potential level to keep the first transistor remaining turned off. The circuit further includes a device for restricting current flow from the output terminal to the predetermined potential side through the first and second transistors.

摘要翻译： 低压输出电路具有第一和第二MOS晶体管。 输入信号被馈送到第一晶体管的栅极。 第一晶体管的源极和漏极之一被提供预定电位。 另一个连接到输出端子并产生输出信号。 第一晶体管响应于输入信号将输出信号提高到预定电位电平。 第二MOS晶体管的源极和漏极之一连接到第一晶体管的栅极。 另一个连接到输出端子。 该电路还包括用于向第二晶体管的栅极提供偏置电压的装置，使得第一和第二晶体管在不同的栅极偏置电位下保持截止，并且当输出信号升高到第一晶体管时，第二晶体管导通 保持第一晶体管保持关闭的预定电位电平。 电路还包括用于限制通过第一和第二晶体管从输出端到预定电位侧的电流的装置。

公开(公告)号：US20100259526A1

公开(公告)日：2010-10-14

申请号：US12793730

申请日：2010-06-04

申请人： Kenji Shino ,  Yasukazu Noine

发明人： Kenji Shino ,  Yasukazu Noine

IPC分类号： G06F3/038 ,  G09G3/36

CPC分类号： G09G3/22 ,  G09G2300/06 ,  G09G2310/0267 ,  G09G2320/0209 ,  G09G2320/0223

摘要： A scanning circuit having a plurality of output units each outputs an ON potential sequentially, comprises: a first output unit that changes an ON potential to an OFF potential during a first period; and a second output unit that changes the OFF potential to the ON potential during a second period, wherein at least part of the first period and at least part of the second period overlap.

摘要翻译： 具有多个输出单元的扫描电路各自依次输出ON电位，包括：第一输出单元，其在第一周期期间将ON电位改变为OFF电位; 以及第二输出单元，其在第二时段期间将所述OFF电位改变为ON电位，其中所述第一周期的至少一部分和所述第二周期的至少部分重叠。