利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.02 秒)

    Spread-spectrum demodulator
    2.
    发明授权
    Spread-spectrum demodulator 有权
    扩频解调器

    公开(公告)号：US07430233B2

    公开(公告)日：2008-09-30

    申请号：US10726371

    申请日：2003-12-02

    申请人： Kenji Suzuki ,  Mamoru Ugajin ,  Tsuneo Tsukahara

    发明人： Kenji Suzuki ,  Mamoru Ugajin ,  Tsuneo Tsukahara

    IPC分类号： H04B1/00

    CPC分类号： H04J13/10 ,  H04B1/70756 ,  H04B2201/70707

    摘要： A spread-spectrum demodulator includes a spreading code generating section, correlation value computing section, data signal demodulating section, peak signal detecting section, and spreading code generation control section. The spreading code generating section generates a spreading code for correlating with a received spread signal. The correlation value computing section computes a correlation value between the spread signal and the spreading code output from the spreading code generating section. The data signal demodulating section detects the peak of an output from the correlation value computing section and demodulates a data signal on the basis of the detected peak. The peak signal detecting section detects the peak of the output from the correlation value computing section. The spreading code generation control section changes the shifting direction of the spreading code relative to the spread signal every time a peak is detected by the peak signal detecting section.

    摘要翻译： 扩频解调器包括扩展码产生部分，相关值计算部分，数据信号解调部分，峰值信号检测部分和扩展码产生控制部分。 扩展码产生部分产生用于与接收的扩展信号相关的扩展码。 相关值计算部分计算扩展信号和从扩展码产生部分输出的扩展码之间的相关值。 数据信号解调部分检测来自相关值计算部分的输出的峰值，并且基于检测到的峰值解调数据信号。 峰值信号检测部分检测来自相关值计算部分的输出的峰值。 每当由峰值信号检测部检测到峰值时，扩展码产生控制部分改变扩展码相对于扩展信号的移位方向。

    Fractional-N frequency divider system
    6.
    发明授权
    Fractional-N frequency divider system 失效
    分数N分频器系统

    公开(公告)号：US5714896A

    公开(公告)日：1998-02-03

    申请号：US608559

    申请日：1996-02-28

    申请人： Tadao Nakagawa ,  Tsuneo Tsukahara ,  Masao Suzuki ,  Tsutomu Kamoto

    发明人： Tadao Nakagawa ,  Tsuneo Tsukahara ,  Masao Suzuki ,  Tsutomu Kamoto

    IPC分类号： G06F7/68 ,  H03K23/64 ,  H03K23/68 ,  H03L7/183 ,  H03L7/197 ,  H03K21/00

    CPC分类号： H03L7/1974 ,  G06F7/68 ,  H03K23/68

    摘要： A fractional-N frequency divider system generates an output signal having frequency of an input signal divided by a desired frequency division ratio (N+A/M) in which N is an integer and A/M is a fraction, A.ltoreq.M, and includes a programmable frequency divider receiving input frequency and providing divided frequency in which division ratio (N, N+1) is an integer and is externally supplied, a selector supplying one of the externally supplied integers (N, N+1) to the divider according to a selection signal, and a fractional part set having a first counter initialized to count M, a second counter initialized to count A, and a logic circuit for supplying the selection signal according to the counters. The counters are decremented by an output of the divider and reach zero when they receive M and A number of pulses, respectively. The second counter stops counting operation when it reaches zero. The logic circuit makes the selector select an integer N in a condition when content of the first counter is not zero and content of the second counter is zero, and N+1 in other conditions, so that the division ratio in the divider is N+1 for A number of output pulses of the divider among M number of output pulses, and is N for M-A number of the output pulses.

    摘要翻译： 分数N分频器系统产生输出信号的频率除以N为整数且A / M为分数的期望分频比（N + A / M）的输入信号，A = M ，并且包括可编程分频器，其接收输入频率并提供分频比（N，N + 1）为整数并被外部提供的分频，选择器将外部提供的整数（N，N + 1）中的一个提供给 根据选择信号的分频器，以及具有初始化为计数M的第一计数器的初始化计数器A的第二计数器和用于根据计数器提供选择信号的逻辑电路的分数部分组。 计数器通过分频器的输出递减，当它们分别接收到M和A个脉冲时，它们达到零。 第二个计数器在零到达时停止计数操作。 逻辑电路使选择器在第一计数器的内容不为零并且第二计数器的内容为零并且在其他条件下为N + 1的条件中选择整数N，使得分频器中的分频比为N + 1表示M个输出脉冲之间的分频器的输出脉冲数，M为输出脉冲的N为N。

    Phase locked loop
    7.
    发明授权
    Phase locked loop 失效
    锁相环

    公开(公告)号：US06759912B2

    公开(公告)日：2004-07-06

    申请号：US10254973

    申请日：2002-09-26

    申请人： Akihiro Yamagishi ,  Tsuneo Tsukahara

    发明人： Akihiro Yamagishi ,  Tsuneo Tsukahara

    IPC分类号： H03L700

    CPC分类号： H03L7/0895 ,  H03L7/14 ,  H03L7/18

    摘要： A phase-locked loop comprises a phase detector receiving an externally supplied reference signal and a feedback signal, a charge pump connected to an output of the phase detector, a loop filter configured to extract a low-frequency component from an output of the charge pump, and a voltage controlled oscillator having an input connected to the output of the loop filter and an output connected to the feedback signal supplied to the phase detector. The charge pump comprises a first switch that controls outputting a positive current based on the output of the phase detector, a second switch that controls outputting a negative current based on the output of the phase detector, a third switch connected between the first switch and the second switch to control an output to the loop filter, and a switching control signal input terminal that receives a switching control signal for controlling a switching operation of the third switch.

    摘要翻译： 锁相环包括接收外部提供的参考信号和反馈信号的相位检测器，连接到相位检测器的输出的电荷泵，配置成从电荷泵的输出中提取低频分量的环路滤波器 以及压控振荡器，其具有连接到环路滤波器的输出的输入端和连接到提供给相位检测器的反馈信号的输出。 电荷泵包括第一开关，其基于相位检测器的输出控制输出正电流;第二开关，其基于相位检测器的输出控制输出负电流;第三开关，连接在第一开关和第二开关之间; 用于控制到环路滤波器的输出的第二开关，以及接收用于控制第三开关的开关操作的开关控制信号的开关控制信号输入端子。

    Image-rejection receiver
    8.
    发明授权
    Image-rejection receiver 失效
    图像拒绝接收器

    公开(公告)号：US06516186B1

    公开(公告)日：2003-02-04

    申请号：US09401803

    申请日：1999-09-22

    申请人： Akihiro Yamagishi ,  Tsuneo Tsukahara ,  Mitsuru Harada

    发明人： Akihiro Yamagishi ,  Tsuneo Tsukahara ,  Mitsuru Harada

    IPC分类号： A04B110

    CPC分类号： H03D3/007

    摘要： In an image-rejection receiver having a first frequency conversion stage (1, 2, 9) having a pair of frequency mixers (1,2) each supplied external radio frequency signal (RF) and first local frequency signal (LOCAL1) with quadrature phase relations (9), a second frequency conversion stage (3-6, 10) having two pairs of frequency mixers (3-4, 5-6) at each output of each first stage mixer and second local frequency signal (LOCAL2) with quadrature phase relations (10), and an adder (7) and a subtractor (8) for providing sum and difference of amplitude of outputs of said second frequency conversion stage to provide inphase component (BBI) and quadrature-phase component (BBQ), no filter is used for removing an undesirable image signal which is generated in frequency conversion. A control circuit (11) is provided to keep accurate quadrature phase relations for said first local frequency signal, and said second local frequency signal, by measuring D.C. component of a product of outputs of two of mixers.

    摘要翻译： 在具有第一频率转换级（1,2,9）的镜像抑制接收机中，所述第一频率转换级具有一对频率混合器（1,2），每个频率混合器提供外部射频信号（RF）和具有正交相位的第一本地频率信号（LOCAL1） 关系（9），在每个第一级混合器的每个输出处具有两对混频器（3-4,5-6）和具有正交的第二本地频率信号（LOCAL2）的第二频率转换级（3-6,10） 相位关系（10）和用于提供所述第二频率转换级的输出的幅度的和差和加法器（7）和减法器（8）以提供同相分量（BBI）和正交相分量（BBQ），否则 滤波器用于去除在频率转换中产生的不期望的图像信号。 提供控制电路（11），通过测量两个混频器的输出的乘积的直流分量来保持所述第一本地频率信号和所述第二本地频率信号的精确正交相位关系。

    Quadrature signal generation system
    9.
    发明授权
    Quadrature signal generation system 失效
    正交信号发生系统

    公开(公告)号：US06369633B1

    公开(公告)日：2002-04-09

    申请号：US09619637

    申请日：2000-07-19

    申请人： Tsuneo Tsukahara

    发明人： Tsuneo Tsukahara

    IPC分类号： H03H1116

    CPC分类号： H03B27/00 ,  H03C3/40

    摘要： A quadrature signal generation system which has a pair of input terminals for receiving a first A.C. signal and a second A.C. signal. The first A.C. signal and the second A.C. signal have a predetermined frequency and a phase relation of approximate 90° with each other. The system also has a multiplier circuit for providing a product of the first A.C. signal and the second A.C. signal, resulting in a third A.C. signal. Furthermore, the system has a square-difference circuit for providing a difference of a square of the first A.C. signal and a square of the second A.C. signal, the difference being a fourth A.C. signal. The frequency of the third A.C. signal, and the fourth A.C. signal are equal to twice the frequency of the first A.C. signal and the second A.C. signal, and the third A.C. signal and the fourth A.C. signal have a fine phase relation of 90° with each other.

    摘要翻译： 一种正交信号发生系统，其具有用于接收第一交流信号和第二交流信号的一对输入端。 第一交流信号和第二交流信号具有预定的频率和大约90°的相位关系。 该系统还具有乘法器电路，用于提供第一交流信号和第二交流信号的乘积，产生第三交流信号。 此外，该系统具有平方差电路，用于提供第一交点信号的平方和第二交点信号的平方的差，该差是第四交点信号。 第三交流信号和第四交流信号的频率等于第一交流信号和第二交流信号的频率的两倍，并且第三交流信号和第四交流信号与每个信号具有90°的精细相位关系 其他。

    Two-modulus prescaler circuit
    10.
    发明申请
    Two-modulus prescaler circuit 审中-公开
    双模预分频电路

    公开(公告)号：US20050116258A1

    公开(公告)日：2005-06-02

    申请号：US10499640

    申请日：2002-12-17

    申请人： Akihiro Yamagishi ,  Tsuneo Tsukahara ,  Yukio Shimpo

    发明人： Akihiro Yamagishi ,  Tsuneo Tsukahara ,  Yukio Shimpo

    IPC分类号： H03K21/00 ,  H03K23/64 ,  H03K23/66 ,  H01L29/768

    CPC分类号： H03K23/667

    摘要： In the dual modulus prescaler circuit, an output terminal of the first multi-input logic gate circuit is connected to a data input terminal of a first D flip-flop circuit; output terminals of the first to (n-2)th D flip-flop circuits are, respectively, connected to data input terminals of the second to (n-1)th D flip-flop circuits; output terminals of the (n-1)th and nth D flip-flop circuits are connected to input terminals of the first multi-input logic gate circuit; the second multi-input logic gate circuit is connected to the output terminal of the (n-1)th D flip-flop circuit and receives a switching signal; and an output terminal of the second multi-input logic gate circuit is connected to a data input terminal of the nth D flip-flop circuit. Moreover, all the aforementioned connections are connections using differential signals.

    摘要翻译： 在双模预分频器电路中，第一多输入逻辑门电路的输出端连接到第一D触发器电路的数据输入端; 第一至第（n-2）D个触发器电路的输出端分别连接到第二至第（n-1）D个触发器电路的数据输入端; 第（n-1）和第n D触发器电路的输出端连接到第一多输入逻辑门电路的输入端; 第二多输入逻辑门电路连接到第（n-1）D触发器电路的输出端，并接收切换信号; 并且第二多输入逻辑门电路的输出端连接到第n D触发器电路的数据输入端。 此外，所有上述连接都是使用差分信号的连接。