公开(公告)号：US07940570B2

公开(公告)日：2011-05-10

申请号：US12494104

申请日：2009-06-29

申请人： Kenta Kato ,  Masahiro Niimi ,  Koji Shimbayashi

发明人： Kenta Kato ,  Masahiro Niimi ,  Koji Shimbayashi

IPC分类号： G11C16/04 ,  G11C7/02

CPC分类号： G11C7/14 ,  G11C16/28

摘要： A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.

摘要翻译： 使用单独的动态参考（Dref）区域来提供阈值电压参考信号的存储器。 存储器包括单独的Dref区域，位于Dref区域之间的数据区域，参考阵列和一个或多个读出放大器。 数据区被配置为提供输出信号，参考单元和单独的D ref区域被布置成提供阈值电压参考信号，并且读出放大器布置成接收输出信号和阈值电压参考信号。

公开(公告)号：US20100329003A1

公开(公告)日：2010-12-30

申请号：US12494114

申请日：2009-06-29

申请人： Kenta Kato ,  Masahiro Niimi ,  Koji Shimbayashi

发明人： Kenta Kato ,  Masahiro Niimi ,  Koji Shimbayashi

IPC分类号： G11C16/06 ,  G11C7/02

CPC分类号： G11C16/28 ,  G11C7/14

摘要： A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.

摘要翻译： 采用独立访问的独立Dref区域以提供阈值电压参考信号的存储器。 存储器包括单独的Dref区域，位于Dref区域之间的数据区域，一个或多个读出放大器和开关组件。 开关部件布置成接收寻址数据，并且至少部分地基于单个存储器单元沿着字线的物理接近度将独立的Dref区域独立地耦合到读出放大器。

公开(公告)号：US07961519B2

公开(公告)日：2011-06-14

申请号：US12494114

申请日：2009-06-29

申请人： Kenta Kato ,  Masahiro Niimi ,  Koji Shimbayashi

发明人： Kenta Kato ,  Masahiro Niimi ,  Koji Shimbayashi

IPC分类号： G11C16/06 ,  G11C7/02

CPC分类号： G11C16/28 ,  G11C7/14

摘要： A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.

摘要翻译： 采用独立访问的独立Dref区域以提供阈值电压参考信号的存储器。 存储器包括单独的Dref区域，位于Dref区域之间的数据区域，一个或多个读出放大器和开关组件。 开关部件布置成接收寻址数据，并且至少部分地基于单个存储器单元沿着字线的物理接近度将独立的Dref区域独立地耦合到读出放大器。

公开(公告)号：US20100329024A1

公开(公告)日：2010-12-30

申请号：US12494104

申请日：2009-06-29

申请人： Kenta Kato ,  Masahiro Niimi ,  Koji Shimbayashi

发明人： Kenta Kato ,  Masahiro Niimi ,  Koji Shimbayashi

IPC分类号： G11C16/06 ,  G11C7/02

CPC分类号： G11C7/14 ,  G11C16/28

摘要： A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.

摘要翻译： 使用单独的动态参考（Dref）区域来提供阈值电压参考信号的存储器。 存储器包括单独的Dref区域，位于Dref区域之间的数据区域，参考阵列和一个或多个读出放大器。 数据区被配置为提供输出信号，参考单元和单独的D ref区域被布置成提供阈值电压参考信号，并且读出放大器布置成接收输出信号和阈值电压参考信号。

公开(公告)号：US20080155217A1

公开(公告)日：2008-06-26

申请号：US11644161

申请日：2006-12-22

申请人： Kenta Kato ,  Masahiko Okura ,  Kenji Shibata ,  Mitsuhiro Nagao ,  Stewart Wang

发明人： Kenta Kato ,  Masahiko Okura ,  Kenji Shibata ,  Mitsuhiro Nagao ,  Stewart Wang

IPC分类号： G06F12/14

CPC分类号： G06F12/1425 ,  G06F2212/2022

摘要： A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being not protected; an address change circuit that changes an address in an address space of the first memory region and the second memory region in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting period.

摘要翻译： 半导体器件包括：包括非易失性存储器单元的存储单元阵列; 位于所述存储单元阵列中的第一存储器区域和第二存储器区域，所述第一存储器区域在保护期间被保护，所述第二存储器区域不被保护; 在保护期间，将存储单元阵列中的第一存储器区域和第二存储器区域的地址空间中的地址改变为第二存储器区域的地址空间中的地址的地址改变电路; 以及控制电路，其在保护期间禁止对第一存储区域的访问，并允许访问第二区域。

公开(公告)号：US20060250167A1

公开(公告)日：2006-11-09

申请号：US11482129

申请日：2006-07-07

申请人： Kenta Kato ,  Satoru Kawamoto

发明人： Kenta Kato ,  Satoru Kawamoto

IPC分类号： H03K5/22

CPC分类号： H03K5/08 ,  G01R19/16519 ,  G11C5/143 ,  G11C16/30

摘要： A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

公开(公告)号：US07490192B2

公开(公告)日：2009-02-10

申请号：US11192562

申请日：2005-07-29

申请人： Satoru Sugimoto ,  Kenta Kato

发明人： Satoru Sugimoto ,  Kenta Kato

IPC分类号： G06F13/00

CPC分类号： G11C7/24 ,  G11C7/1078 ,  G11C7/109 ,  G11C16/06 ,  G11C16/22

摘要： In inputting control information for setting access conditions in a system having a common data bus (3), when a predetermined bit string making up an access condition setting command is inputted to predetermined terminals which are not data input/output terminals (S3), the predetermined terminals are set as control information input terminals (S5) and inputted control information is temporarily maintained in a non-volatile memory device (S13). When inputting of control information is completed (S15), the control information that has been temporarily maintained is stored in a non-volatile memory region all at once (S17). During an access condition setting operation, the data input/output terminals are released (S7) and the data bus (3) is made available to other banks or devices (2) so that data transfer efficiency of the system can be improved.

摘要翻译： 在输入具有公共数据总线（3）的系统中设定存取条件的控制信息时，当构成访问条件设定指令的规定位串被输入到不是数据输入输出端子的规定端子（S3）时， 将预定端子设置为控制信息输入端子（S5），并将输入的控制信息暂时保持在非易失性存储器件中（S13）。 当控制信息的输入完成（S15）时，暂时保持的控制信息一次存储在非易失性存储区域（S17）。 在访问条件设置操作期间，数据输入/输出端被释放（S7），数据总线（3）可用于其他存储体或设备（2），从而可以提高系统的数据传输效率。

公开(公告)号：US07082077B2

公开(公告)日：2006-07-25

申请号：US10635431

申请日：2003-08-07

申请人： Kenta Kato

发明人： Kenta Kato

IPC分类号： G11C8/00

CPC分类号： G11C7/02 ,  G11C7/22 ,  G11C16/30 ,  G11C16/32 ,  G11C2207/2281 ,  G11C2207/229

摘要： A control method of a semiconductor memory device which enables control of an operation mode including an operation that might become a noise source by using an operation mode including an operation from which the influence of noise should be eliminated, and a semiconductor memory device are provided. First and second operation sections performing independent operations are provided, and a signal output section for outputting a second signal S2 and a mode controller section for supplying a control signal C1 are provided in the second operation section. The control signal C1 is outputted from the mode controller section and the signal output section outputs the second signal S2 to a memory cell array, thus performing a second operation. A predetermined first signal SS1 is supplied to the signal output section from the first operation section, thus delaying an output response of a predetermined second signal. While the control signal C1 is outputted from the mode controller section, the supply of the predetermined second signal to the memory cell array can be delayed. The influence of state transition in the second operation on the operation state of the first operation can be eliminated.

摘要翻译： 一种半导体存储器件的控制方法，其能够通过使用包括应该消除噪声的影响的操作的操作模式和半导体存储器件来实现包括可能成为噪声源的操作的操作模式。 提供执行独立操作的第一和第二操作部分，并且在第二操作部分中提供用于输出第二信号S 2的信号输出部分和用于提供控制信号C1的模式控制器部分。 控制信号C 1从模式控制器部分输出，信号输出部分将第二信号S 2输出到存储单元阵列，从而执行第二操作。 预定的第一信号SS 1从第一操作部分提供给信号输出部分，从而延迟预定第二信号的输出响应。 当控制信号C 1从模式控制器部分输出时，可以延迟向存储单元阵列提供预定的第二信号。 可以消除第二操作中的状态转移对第一操作的操作状态的影响。

公开(公告)号：US20060023500A1

公开(公告)日：2006-02-02

申请号：US11194111

申请日：2005-07-28

申请人： Shozo Kawabata ,  Takaaki Furuyama ,  Kenta Kato

发明人： Shozo Kawabata ,  Takaaki Furuyama ,  Kenta Kato

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C7/20 ,  G11C16/20 ,  G11C16/26 ,  G11C16/344

摘要： When an initializing operation starts, a busy state indicative of the disenable of access operation is set (S11), and read operation information is read out by preferentially using a verify sense amplifier 4 or a high-speed read sense amplifier 3 (S12). Upon completion of latching the read operation information (S13: Y), a ready state that announces that the read access operation from a non-redundant memory region is enabled is set (S14), and a ready signal is outputted according to an external read access request to the non-redundant memory region. A boot program or the like which is in the non-redundant memory region can be read out in parallel with the read of the operation information. Subsequently, the redundancy information is read out (S15), and a ready state that announces that the read access operation from all of the memory regions is enabled is set upon completion of reading out the redundancy information (S17). Thereafter, rewrite operation information is read out (S18). The period of time since the start of the initializing operation to the start of the read access operation can thereby be reduced.

摘要翻译： 当初始化操作开始时，设定指示无法访问操作的忙碌状态（S11），并通过优先使用校验读出放大器4或高速读出放大器3读出读操作信息（S12） ）。 在完成对读取操作信息的锁存（S13：Y）时，设定了从非冗余存储器区域通知读取操作的就绪状态（S14），并且根据 外部读取访问请求到非冗余存储器区域。 在非冗余存储器区域中的引导程序等可以与操作信息的读取并行地读出。 随后，读取冗余信息（S17），读出冗余信息（S15），并且在完成读取冗余信息时设置宣告来自所有存储区域的读取访问操作的就绪状态。 此后，读出重写操作信息（S18）。 因此，可以减少从初始化操作开始到读取访问操作开始的时间段。

公开(公告)号：US20050134326A1

公开(公告)日：2005-06-23

申请号：US11057143

申请日：2005-02-15

申请人： Kenta Kato ,  Satoru Kawamoto

发明人： Kenta Kato ,  Satoru Kawamoto

IPC分类号： G01R19/165 ,  G11C5/14 ,  G11C16/30 ,  H03K5/08 ,  H03K5/153

CPC分类号： H03K5/08 ,  G01R19/16519 ,  G11C5/143 ,  G11C16/30

摘要： A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

摘要翻译： 一种电压检测电路，用于在抑制由晶体管的漏电流引起的电压波动的同时精确地检测电压。 电压检测电路包括第一和第二电容器，第一和第二晶体管，比较器和控制电路。 电容器串联连接以产生对应于电容器的高电压的分压。 当晶体管被激活时，第一电容器和第二电容器之间的节点处的电位被复位为接地电位。 当节点处的电位达到预定电位时，第一晶体管失活，然后第二晶体管失活。