公开(公告)号：US20060023500A1

公开(公告)日：2006-02-02

申请号：US11194111

申请日：2005-07-28

申请人： Shozo Kawabata ,  Takaaki Furuyama ,  Kenta Kato

发明人： Shozo Kawabata ,  Takaaki Furuyama ,  Kenta Kato

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C7/20 ,  G11C16/20 ,  G11C16/26 ,  G11C16/344

摘要： When an initializing operation starts, a busy state indicative of the disenable of access operation is set (S11), and read operation information is read out by preferentially using a verify sense amplifier 4 or a high-speed read sense amplifier 3 (S12). Upon completion of latching the read operation information (S13: Y), a ready state that announces that the read access operation from a non-redundant memory region is enabled is set (S14), and a ready signal is outputted according to an external read access request to the non-redundant memory region. A boot program or the like which is in the non-redundant memory region can be read out in parallel with the read of the operation information. Subsequently, the redundancy information is read out (S15), and a ready state that announces that the read access operation from all of the memory regions is enabled is set upon completion of reading out the redundancy information (S17). Thereafter, rewrite operation information is read out (S18). The period of time since the start of the initializing operation to the start of the read access operation can thereby be reduced.

摘要翻译： 当初始化操作开始时，设定指示无法访问操作的忙碌状态（S11），并通过优先使用校验读出放大器4或高速读出放大器3读出读操作信息（S12） ）。 在完成对读取操作信息的锁存（S13：Y）时，设定了从非冗余存储器区域通知读取操作的就绪状态（S14），并且根据 外部读取访问请求到非冗余存储器区域。 在非冗余存储器区域中的引导程序等可以与操作信息的读取并行地读出。 随后，读取冗余信息（S17），读出冗余信息（S15），并且在完成读取冗余信息时设置宣告来自所有存储区域的读取访问操作的就绪状态。 此后，读出重写操作信息（S18）。 因此，可以减少从初始化操作开始到读取访问操作开始的时间段。

公开(公告)号：US07415568B2

公开(公告)日：2008-08-19

申请号：US11194111

申请日：2005-07-28

申请人： Shozo Kawabata ,  Takaaki Furuyama ,  Kenta Kato

发明人： Shozo Kawabata ,  Takaaki Furuyama ,  Kenta Kato

IPC分类号： G11C16/02

CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C7/20 ,  G11C16/20 ,  G11C16/26 ,  G11C16/344

摘要： When an initializing operation starts, a busy state indicative of the disenable of access operation is set (S11), and read operation information is read out by preferentially using a verify sense amplifier 4 or a high-speed read sense amplifier 3 (S12). Upon completion of latching the read operation information (S13: Y), a ready state that announces that the read access operation from a non-redundant memory region is enabled is set (S14), and a ready signal is outputted according to an external read access request to the non-redundant memory region. A boot program or the like which is in the non-redundant memory region can be read out in parallel with the read of the operation information. Subsequently, the redundancy information is read out (S15), and a ready state that announces that the read access operation from all of the memory regions is enabled is set upon completion of reading out the redundancy information (S17). Thereafter, rewrite operation information is read out (S18). The period of time since the start of the initializing operation to the start of the read access operation can thereby be reduced.

摘要翻译： 当初始化操作开始时，设定指示无法访问操作的忙碌状态（S11），并通过优先使用校验读出放大器4或高速读出放大器3读出读操作信息（S12） ）。 在完成对读取操作信息的锁存（S13：Y）时，设定了从非冗余存储器区域通知读取操作的就绪状态（S14），并且根据 外部读取访问请求到非冗余存储器区域。 在非冗余存储器区域中的引导程序等可以与操作信息的读取并行地读出。 随后，读取冗余信息（S17），读出冗余信息（S15），并且在完成读取冗余信息时设置宣告来自所有存储区域的读取访问操作的就绪状态。 此后，读出重写操作信息（S18）。 因此，可以减少从初始化操作开始到读取访问操作开始的时间段。

公开(公告)号：US07239548B2

公开(公告)日：2007-07-03

申请号：US11317082

申请日：2005-12-21

申请人： Kenta Kato ,  Takaaki Furuyama

发明人： Kenta Kato ,  Takaaki Furuyama

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C29/1201 ,  G11C5/14 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/50004 ,  G11C29/82 ,  G11C2029/5006

摘要： In Step 1, a bias is applied (ON) to all of vertical rows Z1(0) to Z1(2). With respect to the horizontal rows, a bias is not applied (OFF) to a horizontal row Z2(0) where the defective sector exists and a bias is applied (ON) to the other horizontal rows Z2(1) and Z2(2). On the sectors in the horizontal rows Z2(1) and Z2(2), a voltage stress is applied and an access operation is performed. In Step 2, with respect to the vertical rows, a bias is not applied (OFF) to a vertical row Z1(1) where the defective sector exists and a bias is applied (ON) to the other vertical rows Z1(0) and Z1(2). With respect to the horizontal rows, a bias is applied (ON) to the horizontal row Z2(0) where the defective sector exists, and no bias is applied (OFF) to the other horizontal rows Z2(1) and Z2(2). As for the two steps, a voltage stress can be applied once to the sectors other than the defective sector.

摘要翻译： 在步骤1中，对所有垂直行Z 1（0）至Z 1（2）施加偏压（ON）。 相对于水平行，不对缺陷扇区存在并且向其他水平行Z 2（1）和Z 2施加偏压（ON）的水平行Z 2（0）施加偏压（OFF） （2）。 在水平行Z 2（1）和Z 2（2）的扇区上施加电压应力并进行存取操作。 在步骤2中，相对于垂直列，不对垂直行Z 1（1）施加偏压，其中存在缺陷扇区并且向其它垂直行Z 1（0）施加偏压（ON） ）和Z 1（2）。 对于水平行，对存在缺陷扇区的水平行Z 2（0）施加偏压（ON），并且不向其他水平行Z 2（1）和Z 2施加偏压（OFF） （2）。 对于两个步骤，可以对除了缺陷扇区之外的扇区施加一次电压应力。

公开(公告)号：US20060227630A1

公开(公告)日：2006-10-12

申请号：US11317082

申请日：2005-12-21

申请人： Kenta Kato ,  Takaaki Furuyama

发明人： Kenta Kato ,  Takaaki Furuyama

IPC分类号： G11C5/14

CPC分类号： G11C29/1201 ,  G11C5/14 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/50004 ,  G11C29/82 ,  G11C2029/5006

摘要： In Step 1, a bias is applied (ON) to all of vertical rows Z1(0) to Z1(2). With respect to the horizontal rows, a bias is not applied (OFF) to a horizontal row Z2(0) where the defective sector exists and a bias is applied (ON) to the other horizontal rows Z2(1) and Z2(2). On the sectors in the horizontal rows Z2(1) and Z2(2), a voltage stress is applied and an access operation is performed. In Step 2, with respect to the vertical rows, a bias is not applied (OFF) to a vertical row Z1(1) where the defective sector exists and a bias is applied (ON) to the other vertical rows Z1(0) and Z1(2). With respect to the horizontal rows, a bias is applied (ON) to the horizontal row Z2(0) where the defective sector exists, and no bias is applied (OFF) to the other horizontal rows Z2(1) and Z2(2). As for the two steps, a voltage stress can be applied once to the sectors other than the defective sector.

摘要翻译： 在步骤1中，对所有垂直行Z 1（0）至Z 1（2）施加偏压（ON）。 相对于水平行，不对缺陷扇区存在并且向其他水平行Z 2（1）和Z 2施加偏压（ON）的水平行Z 2（0）施加偏压（OFF） （2）。 在水平行Z 2（1）和Z 2（2）的扇区上施加电压应力并进行存取操作。 在步骤2中，相对于垂直列，不对垂直行Z 1（1）施加偏压，其中存在缺陷扇区并且向其它垂直行Z 1（0）施加偏压（ON） ）和Z 1（2）。 对于水平行，对存在缺陷扇区的水平行Z 2（0）施加偏压（ON），并且不向其他水平行Z 2（1）和Z 2施加偏压（OFF） （2）。 对于两个步骤，可以对除了缺陷扇区之外的扇区施加一次电压应力。

公开(公告)号：US07120050B2

公开(公告)日：2006-10-10

申请号：US11259873

申请日：2005-10-26

申请人： Shozo Kawabata ,  Mitsuhiro Nagao ,  Kenta Kato

发明人： Shozo Kawabata ,  Mitsuhiro Nagao ,  Kenta Kato

IPC分类号： G11C16/04

CPC分类号： G11C29/02 ,  G11C16/102 ,  G11C16/20 ,  G11C16/3436 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402

摘要： A verify sense amplifier (19) reads data from a non-volatile memory cell to be rewritten. The readout data is compared to expected data in a comparator circuit (21). Upon completion of rewriting, the comparator circuit (21) outputs a match signal MCH. A selector (23) outputs a decode signal STR(i) or SWP(i) indicative of a volatile data retaining unit (25), in correspondence with the non-volatile memory cell MC to be rewritten. According to a verify instruction signal PGV/ERV, the readout data read by the verify sense amplifier (19) is stored in the volatile data retaining unit (25). Control is performed with a match signal MCH instead of the verify instruction signal PGV/ERV, thereby storing the data in the volatile data retaining unit (25) upon completion of rewriting. Therefore, there is no need to re-read operational information from the non-volatile storage.

公开(公告)号：US20060098496A1

公开(公告)日：2006-05-11

申请号：US11259873

申请日：2005-10-26

申请人： Shozo Kawabata ,  Mitsuhiro Nagao ,  Kenta Kato

发明人： Shozo Kawabata ,  Mitsuhiro Nagao ,  Kenta Kato

IPC分类号： G11C7/10

CPC分类号： G11C29/02 ,  G11C16/102 ,  G11C16/20 ,  G11C16/3436 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402

摘要： A verify sense amplifier (19) reads data from a non-volatile memory cell to be rewritten. The readout data is compared to expected data in a comparator circuit (21). Upon completion of rewriting, the comparator circuit (21) outputs a match signal MCH. A selector (23) outputs a decode signal STR(i) or SWP(i) indicative of a volatile data retaining unit (25), in correspondence with the non-volatile memory cell MC to be rewritten. According to a verify instruction signal PGV/ERV, the readout data read by the verify sense amplifier (19) is stored in the volatile data retaining unit (25). Control is performed with a match signal MCH instead of the verify instruction signal PGV/ERV, thereby storing the data in the volatile data retaining unit (25) upon completion of rewriting. Therefore, there is no need to re-read operational information from the non-volatile storage.

摘要翻译： 验证读出放大器（19）从要被重写的非易失性存储器单元读取数据。 读出数据与比较器电路（21）中的期望数据进行比较。 在完成重写时，比较器电路（21）输出匹配信号MCH。 选择器（23）对应于要重写的非易失性存储器单元MC输出指示易失性数据保持单元（25）的解码信号STR（i）或SWP（i）。 根据验证指示信号PGV / ERV，将由验证读出放大器（19）读出的读出数据存储在易失性数据保持单元（25）中。 通过匹配信号MCH而不是验证指令信号PGV / ERV进行控制，从而在完成重写时将数据存储在易失性数据保持单元（25）中。 因此，不需要从非易失性存储器重新读取操作信息。

公开(公告)号：US20080155217A1

公开(公告)日：2008-06-26

申请号：US11644161

申请日：2006-12-22

申请人： Kenta Kato ,  Masahiko Okura ,  Kenji Shibata ,  Mitsuhiro Nagao ,  Stewart Wang

发明人： Kenta Kato ,  Masahiko Okura ,  Kenji Shibata ,  Mitsuhiro Nagao ,  Stewart Wang

IPC分类号： G06F12/14

CPC分类号： G06F12/1425 ,  G06F2212/2022

摘要： A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being not protected; an address change circuit that changes an address in an address space of the first memory region and the second memory region in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting period.

摘要翻译： 半导体器件包括：包括非易失性存储器单元的存储单元阵列; 位于所述存储单元阵列中的第一存储器区域和第二存储器区域，所述第一存储器区域在保护期间被保护，所述第二存储器区域不被保护; 在保护期间，将存储单元阵列中的第一存储器区域和第二存储器区域的地址空间中的地址改变为第二存储器区域的地址空间中的地址的地址改变电路; 以及控制电路，其在保护期间禁止对第一存储区域的访问，并允许访问第二区域。

公开(公告)号：US20060250167A1

公开(公告)日：2006-11-09

申请号：US11482129

申请日：2006-07-07

申请人： Kenta Kato ,  Satoru Kawamoto

发明人： Kenta Kato ,  Satoru Kawamoto

IPC分类号： H03K5/22

CPC分类号： H03K5/08 ,  G01R19/16519 ,  G11C5/143 ,  G11C16/30

摘要： A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

公开(公告)号：US07940570B2

公开(公告)日：2011-05-10

申请号：US12494104

申请日：2009-06-29

申请人： Kenta Kato ,  Masahiro Niimi ,  Koji Shimbayashi

发明人： Kenta Kato ,  Masahiro Niimi ,  Koji Shimbayashi

IPC分类号： G11C16/04 ,  G11C7/02

CPC分类号： G11C7/14 ,  G11C16/28

摘要： A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.

摘要翻译： 使用单独的动态参考（Dref）区域来提供阈值电压参考信号的存储器。 存储器包括单独的Dref区域，位于Dref区域之间的数据区域，参考阵列和一个或多个读出放大器。 数据区被配置为提供输出信号，参考单元和单独的D ref区域被布置成提供阈值电压参考信号，并且读出放大器布置成接收输出信号和阈值电压参考信号。

公开(公告)号：US07490192B2

公开(公告)日：2009-02-10

申请号：US11192562

申请日：2005-07-29

申请人： Satoru Sugimoto ,  Kenta Kato

发明人： Satoru Sugimoto ,  Kenta Kato

IPC分类号： G06F13/00

CPC分类号： G11C7/24 ,  G11C7/1078 ,  G11C7/109 ,  G11C16/06 ,  G11C16/22

摘要： In inputting control information for setting access conditions in a system having a common data bus (3), when a predetermined bit string making up an access condition setting command is inputted to predetermined terminals which are not data input/output terminals (S3), the predetermined terminals are set as control information input terminals (S5) and inputted control information is temporarily maintained in a non-volatile memory device (S13). When inputting of control information is completed (S15), the control information that has been temporarily maintained is stored in a non-volatile memory region all at once (S17). During an access condition setting operation, the data input/output terminals are released (S7) and the data bus (3) is made available to other banks or devices (2) so that data transfer efficiency of the system can be improved.

摘要翻译： 在输入具有公共数据总线（3）的系统中设定存取条件的控制信息时，当构成访问条件设定指令的规定位串被输入到不是数据输入输出端子的规定端子（S3）时， 将预定端子设置为控制信息输入端子（S5），并将输入的控制信息暂时保持在非易失性存储器件中（S13）。 当控制信息的输入完成（S15）时，暂时保持的控制信息一次存储在非易失性存储区域（S17）。 在访问条件设置操作期间，数据输入/输出端被释放（S7），数据总线（3）可用于其他存储体或设备（2），从而可以提高系统的数据传输效率。