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公开(公告)号：US5200920A
公开(公告)日：1993-04-06
申请号：US759944
申请日：1991-09-17
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454
摘要： A method for programming programmable EPROM elements in programmable logic arrays. Multiple programming passes are made through the array, with the programming pulses decreasing in duration on each pass.
摘要翻译： 用于在可编程逻辑阵列中编程可编程EPROM元件的方法。 通过阵列进行多个编程遍历，编程脉冲在每次通过时持续时间减少。
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公开(公告)号：US6151258A
公开(公告)日：2000-11-21
申请号：US428019
申请日：1999-10-27
IPC分类号： G11C7/10 , G11C7/22 , G11C8/16 , H03K19/177 , G11C7/00
CPC分类号： H03K19/17772 , G11C7/1006 , G11C7/1075 , G11C7/22 , G11C8/16 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/17764 , H03K19/1778 , H03K19/177
摘要： An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.
摘要翻译： 如本文所述的用于实现可重配置逻辑的集成电路，例如现场可编程门阵列（“FPGA”），具有多个多端口存储器块。 存储器具有多个读取端口和多个写入端口。 多端口存储器的每个端口可以配置为与其他端口的宽度和深度独立且独立的宽度和深度。 该存储器还包括用于对存储器的内容进行同步快照或将存储器加载到初始状态的端口。 存储器共享由低级逻辑元件使用的路由线，从而减轻了为了满足存储器需求而向互连网络添加路由线路的需要。
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公开(公告)号：US6034857A
公开(公告)日：2000-03-07
申请号：US893249
申请日：1997-07-16
IPC分类号： H03K19/003 , H03K19/177 , H02H3/00
CPC分类号： H03K19/17772 , H03K19/00315 , H03K19/17744 , H03K19/17764 , H03K19/1778
摘要： An overcurrent protection circuit for input/Output (I/O) buffers for a Field Programmable Gate Array wherein short circuits can be detected and the output current limited so as to avoid damaging the device. I/O buffers having the overcurrent protection circuit can detect a contention between the buffers. In order to eliminate the contention, certain I/O buffers will go into a noncontending state.
摘要翻译： 用于现场可编程门阵列的输入/输出（I / O）缓冲器的过流保护电路，其中可以检测短路并限制输出电流，以避免损坏器件。 具有过电流保护电路的I / O缓冲器可以检测缓冲器之间的争用。 为了消除争用，某些I / O缓冲区将进入非持续状态。
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公开(公告)号：US06317367B1
公开(公告)日：2001-11-13
申请号：US09748088
申请日：2000-12-21
IPC分类号： G11C700
CPC分类号： H03K19/17772 , G11C7/1006 , G11C7/1075 , G11C7/22 , G11C8/16 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has multiple blocks of multiported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multiported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.
摘要翻译： 如本文所述的用于实现可重配置逻辑的集成电路，例如现场可编程门阵列（“FPGA”）具有多个多端口存储器块。 存储器具有多个读取端口和多个写入端口。 多端口存储器的每个端口可以配置为与其他端口的宽度和深度独立且独立的宽度和深度。 该存储器还包括用于对存储器的内容进行同步快照或将存储器加载到初始状态的端口。 存储器共享由低级逻辑元件使用的路由线，从而减轻了为了满足存储器需求而向互连网络添加路由线路的需要。
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公开(公告)号：US5870410A
公开(公告)日：1999-02-09
申请号：US840357
申请日：1997-04-28
IPC分类号： G01R31/28
CPC分类号： G01R31/318516
摘要： An diagnostic interface system for a programmable logic system is disclosed. The diagnostic interface system provides an efficient and flexible mechanism for accessing internal nodes of programmable logic devices (PLDs) to facilitate debugging and troubleshooting of the programmable logic system. The interface system includes a diagnostic data bus connecting external I/O pins to various diagnostic data and address registers that connect to the internal circuitry of a PLD. A diagnostics controller controls the various diagnostic resources in response to user supplied control data.
摘要翻译： 公开了一种用于可编程逻辑系统的诊断接口系统。 诊断接口系统为访问可编程逻辑器件（PLD）的内部节点提供了一种有效且灵活的机制，以便于可编程逻辑系统的调试和故障排除。 接口系统包括将外部I / O引脚连接到各种诊断数据的诊断数据总线和连接到PLD内部电路的地址寄存器。 诊断控制器根据用户提供的控制数据控制各种诊断资源。
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6.发明授权
公开(公告)号：US5359243A
公开(公告)日：1994-10-25
申请号：US49694
申请日：1993-04-16
申请人： Kevin A. Norman
发明人： Kevin A. Norman
IPC分类号： H03K19/0185 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/018521
摘要： A fast TTL to CMOS level converting circuit with reduced standby current is disclosed. A fast first stage CMOS inverter with skewed transistor size ratios is isolated from a large load capacitance by a second inverter. The second inverter connects to the power supply through a depletion mode NMOS transistor. The gate terminal of the depletion mode NMOS transistor is driven by the output of the first inverter. The depletion NMOS disconnects the PMOS transistor of the second inverter from the power supply when the input voltage ranges between the power supply and 2.0 volts, resulting in zero standby current for the second stage. Therefore, the second stage can be made large enough to drive large fanout capacitances without incurring additional standby current.
摘要翻译： 公开了一种具有降低待机电流的快速TTL至CMOS电平转换电路。 具有偏斜晶体管尺寸比的快速第一级CMOS反相器通过第二个反相器与大的负载电容隔离。 第二个反相器通过耗尽型NMOS晶体管连接到电源。 耗尽型NMOS晶体管的栅极端子由第一反相器的输出驱动。 当输入电压在电源和2.0伏特之间时，耗尽型NMOS将第二反相器的PMOS晶体管与电源断开，导致第二级的待机电流为零。 因此，第二级可以做得足够大以驱动大的扇出电容，而不会产生额外的待机电流。
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公开(公告)号：US06353552B2
公开(公告)日：2002-03-05
申请号：US09817951
申请日：2001-03-26
IPC分类号： G11C700
CPC分类号： H03K19/17772 , G11C7/1006 , G11C7/1075 , G11C7/22 , G11C8/16 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory block is coupled to the logic element. The memory block includes a memory storage cell to store a first data bit, a shadow cell to store a second data bit, and a transfer circuit. When a first control line of a transfer circuit is asserted, the second bit is transferred from the shadow cell to the memory storage cell. When a second control line of the transfer circuit is asserted, the first bit is transferred from the memory storage cell to the shadow cell.
摘要翻译： 用于初始化和确定可编程逻辑器件中的存储器块的内容的方法和装置。 一种装置包括可编程地配置为实现用户定义的组合或注册的逻辑功能的逻辑元件以及用于存储数据的存储器块。 存储器块耦合到逻辑元件。 存储块包括存储第一数据位的存储器存储单元，用于存储第二数据位的阴影单元和传输电路。 当传送电路的第一控制线被断言时，第二位从影子单元传送到存储器存储单元。 当传输电路的第二控制线被断言时，第一位从存储器存储单元传送到阴影单元。
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公开(公告)号：US6020758A
公开(公告)日：2000-02-01
申请号：US615341
申请日：1996-03-11
申请人： Rakesh H. Patel , Kevin A. Norman
发明人： Rakesh H. Patel , Kevin A. Norman
IPC分类号： H03K19/177 , H03K19/173 , H03K7/38
CPC分类号： H03K19/17752 , H03K19/17756
摘要： Various embodiments of a programmable logic device (PLD) capable of being dynamically partially reconfigured are disclosed. The PLD provides circuitry for changing its configuration data in whole or in part without halting the operation nor losing any of the logic state of the PLD. In one embodiment, data injection circuitry are added to a FIFO architecture to allow the user to inject data at random locations without disturbing the functionality of the PLD. In another embodiment, the PLD architecture is designed to provide for address wide or frame wide accessing of configuration bits. This allows for address wide configuration and reconfiguration.
摘要翻译： 公开了能够动态部分重新配置的可编程逻辑器件（PLD）的各种实施例。 PLD提供用于全部或部分更改其配置数据的电路，而不会停止操作，也不会丢失PLD的任何逻辑状态。 在一个实施例中，将数据注入电路添加到FIFO架构以允许用户在随机位置注入数据而不会干扰PLD的功能。 在另一个实施例中，PLD架构被设计为提供配置位的地址宽或帧宽访问。 这允许地址宽配置和重新配置。
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公开(公告)号：US5693540A
公开(公告)日：1997-12-02
申请号：US656448
申请日：1996-05-31
IPC分类号： H01L21/8247 , H01L27/02 , H01L21/00
CPC分类号： H01L27/11519 , H01L27/0207 , H01L27/11517
摘要： A method of fabricating integrated circuits is provided that allows new integrated circuits to be fabricated with reduced die areas and reduced power consumptions relative to old integrated circuits. The new circuits are interchangeable with the old integrated circuits, because the delay times for the data pathways through the new circuits are the same as the delay times for the data pathways through the old circuits. A family of new circuits, each of which is compatible with a corresponding one of a series of old circuits, can be fabricated using a common circuit layout. Each new circuit is associated with a parameter value that governs the delay time of a component in a data pathway through the circuit and ensures that the new circuit is compatible with the corresponding old circuit.
摘要翻译： 提供了一种制造集成电路的方法，其允许以相对于旧的集成电路减少的芯片面积和降低的功率消耗来制造新的集成电路。 新电路可以与旧的集成电路互换，因为通过新电路的数据通路的延迟时间与通过旧电路的数据通道的延迟时间相同。 可以使用公共电路布局来制造每一个与一系列旧电路中的相应一个电路兼容的新电路系列。 每个新电路与控制通过电路的数据通路中的部件的延迟时间的参数值相关联，并确保新电路与相应的旧电路兼容。
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10.发明授权Method of programming floating gate memory devices aided by potential applied to read channel 失效通过潜在应用于读取通道编程浮动栅格存储器件的方法
公开(公告)号：US5247477A
公开(公告)日：1993-09-21
申请号：US708241
申请日：1991-05-31
申请人： Kevin A. Norman
发明人： Kevin A. Norman
CPC分类号： G11C16/10
摘要： Improved methods of programming floating gate memory devices such as MOS EPROMs having a gate, a floating gate, a read channel, and a write or programming channel. Potential is applied to the read channel (which is normally inactive during programming) in order to increase the voltage induced on the floating gate by the programming voltage applied to the gate. This makes it possible to reduce the programming voltage which must be applied to the gate, to reduce the time required to program the device, or to achieve some measure of both of these benefits.
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