公开(公告)号：US5721864A

公开(公告)日：1998-02-24

申请号：US531948

申请日：1995-09-18

申请人： Kevin Arthur Chiarot ,  Michael John Mayfield ,  Era Kasturia Nangia ,  Milford John Peterson

发明人： Kevin Arthur Chiarot ,  Michael John Mayfield ,  Era Kasturia Nangia ,  Milford John Peterson

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F9/3814 ,  G06F12/0862 ,  G06F9/3802 ,  G06F9/383

摘要： A method for selectively pre-fetching Line M+1 into an L1 instruction cache from an L2 cache or from main memory during the execution of Line M. If unresolved branches exist in pending Line M, Line M+1 is speculative and may be pre-fetched into L1 instruction cache only from L2 cache, not from main memory. Unresolved branches in pending Line M are resolved before Line M+1 is pre-fetched from main memory. If no unresolved branches exist, Line M is committed ("inevitable-speculative") and is pre-fetched from main memory. In this way, no potentially wasteful pre-fetches are performed and main memory bandwidth is preserved.

摘要翻译： 一种用于在线路M执行期间，从L2高速缓存或主存储器中选择性地将线路M + 1预取入L1指令高速缓存。如果在线路M中存在未解决的分支，则线路M + 1是推测性的并且可以是预先 仅从L2缓存中提取到L1指令缓存，而不是从主内存中。 在从主存储器中预取行M + 1之前，解决未决行M中的未解析分支。 如果没有未解决的分支存在，则线M被承诺（“不可避免的推测”），并且从主内存中预取。 以这种方式，不会执行潜在的浪费的预取，并且保留主存储器带宽。

公开(公告)号：US5860150A

公开(公告)日：1999-01-12

申请号：US540374

申请日：1995-10-06

申请人： Kevin Arthur Chiarot ,  Michael John Mayfield ,  Era Kasturia Nangia ,  Milford John Peterson

发明人： Kevin Arthur Chiarot ,  Michael John Mayfield ,  Era Kasturia Nangia ,  Milford John Peterson

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/3802 ,  G06F12/0862

摘要： An apparatus for fetching data from a main memory into a primary cache memory of a processor. Instruction fetch requests are generated by the processor and assigned a priority level according to the predicted accuracy of the fetch request. The priority levels of different fetch requests are compared and the highest priority level fetch request is serviced first. An instruction cache line address N+1 is pre-fetched if there is a cache miss in the primary cache memory on address N+1.

摘要翻译： 一种用于将数据从主存储器读取到处理器的主高速缓冲存储器中的装置。 指令提取请求由处理器产生，并根据提取请求的预测精度分配优先级。 比较不同提取请求的优先级，首先为最高优先级提取请求提供服务。 如果地址N + 1上的主缓存存储器中存在高速缓存未命中，则指令高速缓存行地址N + 1被预取。

公开(公告)号：US06148394A

公开(公告)日：2000-11-14

申请号：US21134

申请日：1998-02-10

申请人： Shih-Hsiung Stephen Tung ,  David Scott Ray ,  Kevin Arthur Chiarot ,  Barry Duane Williamson

发明人： Shih-Hsiung Stephen Tung ,  David Scott Ray ,  Kevin Arthur Chiarot ,  Barry Duane Williamson

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/312

CPC分类号： G06F9/3834 ,  G06F12/0859

摘要： The present invention is directed towards a means to detect and reorder out of order instructions that may violate data coherency. The invention comprises a mis-queue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocesor. The instruction data in each entry comprises: i) address information for the instruction; ii) ordering information for the instruction, indicating the order of the instruction relative to other instructions in the mis-queue table; iii) data modification information for the instruction, for indicating a possibility of modified data; and iv) out of order information, for indicating that a newer instruction has completed before the corresponding older instruction to the entry. The invention also comprises an out of order comparator for comparing an address of a completed instruction to any address information entries in the miss queue. If a completed instruction accesses the same address as another instruction, as indicated in the address information in the mis-queue table, and the completed instruction is newer than the matched instruction, the out of order field is marked indicating this condition exists. The invention comprises a modification comparator. This compares addresses from data altering events to those addresses in the entries in the mis-queue table. On a match, the modification field of the corresponding entry is marked to indicate this condition exists. When an instruction entry indicates that the corresponding instruction's data is modified, and that the instruction is out of order, all subsequent instructions are canceled.

摘要翻译： 本发明涉及一种检测和重新排序可能违反数据一致性的乱序指令的手段。 本发明包括用于保存指令数据条目的错误队列表，每个条目对应于计算机微处理器中的指令。 每个条目中的指令数据包括：i）指令的地址信息; ii）订购指令的信息，指示相对于错误队列表中的其他指令的指令的顺序; iii）指示用于指示修改数据的可能性的数据修改信息; 以及iv）无序信息，用于指示较新的指令在对条目的相应较老指令之前已经完成。 本发明还包括一个无序比较器，用于将完成的指令的地址与未命中队列中的任何地址信息条目进行比较。 如果完成的指令访问与其他指令相同的地址，如错误队列表中的地址信息中所示，并且完成的指令比匹配的指令更新，则会显示乱序字段，指示此条件存在。 本发明包括修改比较器。 这将比较从数据更改事件到错误队列表中条目中的那些地址的地址。 在比赛中，相应条目的修改字段被标记为表示此条件存在。 当指令条目指示对应指令的数据被修改并且指令出现故障时，所有后续指令都被取消。

公开(公告)号：US06622236B1

公开(公告)日：2003-09-16

申请号：US09506229

申请日：2000-02-17

申请人： Kevin Arthur Chiarot ,  Brian R. Konigsburg ,  Dave Stephen Levitan

发明人： Kevin Arthur Chiarot ,  Brian R. Konigsburg ,  Dave Stephen Levitan

IPC分类号： G06F930

CPC分类号： G06F9/3855 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3885

摘要： A microprocessor, data processing system, and an associated method of executing microprocessor instructions and generating instruction fetch addresses are disclosed. The microprocessor includes an instruction fetch unit comprising and instruction fetch address register (IFAR) and an instruction processing unit (IPU). The IFAR is configured to provide an address to an instruction cache. The IPU is suitable for receiving a set of instructions from the instruction cache and for generating an instruction fetch address upon determining from the set of instructions that the program execution flow requires redirection. The IPU is adapted to determine that the program flow requires redirection if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to record the branch instruction information in a single cycle. The IPU may include an address generation unit suitable for generating a set of branch target addresses corresponding to the set of received instructions and a multiplexer configured to receive as inputs the set of branch target addresses. The output of the multiplexer is provided to the instruction address fetch register. The IPU may include an address incrementer suitable for generating a next instruction address corresponding to the next sequential instruction address following the instruction address corresponding to the received set of addresses. In this embodiment, the next instruction address comprises an input to the multiplexer. The IPU may further include selector logic adapted to select the next instruction address as the output of the multiplexer if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to record the branch instruction information in a single cycle. The selector logic is adapted to select as the output of the multiplexer the branch target address of the first instruction predicted to be taken if the number of branch instructions in the set of instructions for which branch instruction information must be recorded does not exceed the capacity of IPU to record the branch instruction information in a single cycle.

公开(公告)号：US6061785A

公开(公告)日：2000-05-09

申请号：US24804

申请日：1998-02-17

申请人： Kevin Arthur Chiarot ,  A. James Van Norstrand, Jr. ,  David Andrew Schroter

发明人： Kevin Arthur Chiarot ,  A. James Van Norstrand, Jr. ,  David Andrew Schroter

IPC分类号： G06F9/305 ,  G06F9/32 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/30094 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855

摘要： An apparatus for condition register (CR) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, logical operations on CR operands may be executed out-of-order using the CR renaming mechanism. Any instruction that updates the CR data has an associated instruction identifier (IID) stored in a register. Subsequent condition register logical (LCR) instructions that use data in the CR use the stored IID to determine when the CR data has been updated by the execution of the instruction corresponding to the stored IID. When an instruction causing a CR data value update finishes executing, the updated data is obtained by snooping the finish bus of the corresponding execution unit. In this way, these instructions can obtain CR data prior to completion of the preceding instructions. Because the updated CR data is available to the LCR next to execute before the updating instruction completes, deserialized execution of LCR instructions is thereby realized.

摘要翻译： 实现了条件寄存器（CR）重命名的装置及其使用方法。 在具有流水线架构的中央处理单元（CPU）中，使用CR重命名机制可以执行对无效操作数的逻辑运算。 更新CR数据的任何指令都具有存储在寄存器中的关联指令标识符（IID）。 使用CR中的数据的后续条件寄存器逻辑（LCR）指令使用存储的IID来确定通过执行与存储的IID相对应的指令来更新CR数据。 当导致CR数据值更新的指令完成执行时，通过窥探相应执行单元的完成总线来获得更新的数据。 以这种方式，这些指令可以在完成前面的指令之前获得CR数据。 因为在更新指令完成之前更新的CR数据可用于下一个执行的LCR，从而实现了反序列化执行LCR指令。

公开(公告)号：US6035394A

公开(公告)日：2000-03-07

申请号：US24805

申请日：1998-02-17

申请人： David Scott Ray ,  Kevin Arthur Chiarot ,  David Andrew Schroter ,  A. James Van Norstrand, Jr. ,  Barry Duane Williamson

发明人： David Scott Ray ,  Kevin Arthur Chiarot ,  David Andrew Schroter ,  A. James Van Norstrand, Jr. ,  Barry Duane Williamson

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and a rename register file. In one particular version of the invention, the method includes the steps of forwarding an instruction from the instruction cache to the sequencing unit operable to access multiple architectural registers; generating a plurality of primitive instructions responsive to the forwarded instruction in which an individual primitive instruction is operable to access an individual architectural register; and sequentially issuing the primitive instructions to move data between the data cache and the rename register file.

摘要翻译： 本发明的一个方面涉及一种用于操作具有指令高速缓存，排序单元，加载/存储单元，高速缓存，架构寄存器文件和重命名寄存器文件的超标量处理器的方法。 在本发明的一个特定版本中，该方法包括以下步骤：将指令从指令高速缓存转发到可操作以访问多个架构寄存器的排序单元; 响应于转发的指令产生多个原语指令，其中单个原语指令可操作以访问单个体系结构寄存器; 并顺序地发出原始指令以在数据高速缓存和重命名寄存器文件之间移动数据。

公开(公告)号：US06332181B1

公开(公告)日：2001-12-18

申请号：US09072324

申请日：1998-05-04

申请人： Douglas Craig Bossen ,  Kevin Arthur Chiarot ,  Namratha Rajasekharaiah Jaisimha ,  Avijit Saha

发明人： Douglas Craig Bossen ,  Kevin Arthur Chiarot ,  Namratha Rajasekharaiah Jaisimha ,  Avijit Saha

IPC分类号： G06F1208

CPC分类号： G06F11/073 ,  G06F11/0793 ,  G06F11/1044 ,  G06F12/0802

摘要： A method of handling a cache error (such as a parity error), which allows a software recovery, by reporting the error using an unrelated system resource, such as an interrupt service, and particularly a data storage interrupt. The parity error can be reported by generating a data storage interrupt and using the data storage interrupt status register (DSISR) to indicate that the data storage interrupt is a result of the parity error. The context of the processor can be fully synchronized while handling the parity error.

摘要翻译： 通过使用诸如中断服务之类的不相关的系统资源（特别是数据存储中断）来报告错误来处理允许软件恢复的高速缓存错误（例如奇偶校验错误）的方法。 可以通过产生数据存储中断并使用数据存储中断状态寄存器（DSISR）来指示数据存储中断是奇偶校验错误的结果来报告奇偶校验错误。 处理器的上下文可以在处理奇偶校验错误的同时完全同步。