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    Regulating unused/inactive resources in programmable logic devices for static power reduction
    1.
    发明授权
    Regulating unused/inactive resources in programmable logic devices for static power reduction 有权
    调节可编程逻辑器件中的未使用/不活动资源以实现静态功耗的降低

    公开(公告)号：US07504854B1

    公开(公告)日：2009-03-17

    申请号：US10783589

    申请日：2004-02-20

    申请人： Kevin T. Look ,  Michael J. Hart ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    发明人： Kevin T. Look ,  Michael J. Hart ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    IPC分类号： H03K19/173 ,  G11C5/14

    CPC分类号： H03K19/1778 ,  G11C5/14 ,  H03K19/17784

    摘要： A method of operating a programmable logic device, including the steps of using a full VDD supply voltage to operate one or more active blocks of the programmable logic device, and using a reduced supply voltage (e.g., ½ VDD) to operate one or more inactive blocks of the programmable logic device. The full VDD supply voltage and reduced supply voltage can be provided to the blocks of the programmable logic device through high-voltage n-channel transistors. A boosted voltage, greater than VDD, is applied to the gate of an n-channel transistor to provide the full VDD supply voltage to an active block. A standby voltage, less than VDD, is applied to the gate of an n-channel transistor to provide the reduced supply voltage to an inactive block. The inactive blocks can be determined during run time and/or design time of the programmable logic device.

    摘要翻译： 一种操作可编程逻辑器件的方法，包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的一个或多个有效块，以及使用降低的电源电压（例如，½VDD）来操作一个或多个不活动的 可编程逻辑器件的块。 可以通过高电压n沟道晶体管向可编程逻辑器件的块提供完整的VDD电源电压和降低的电源电压。 大于VDD的升压电压被施加到n沟道晶体管的栅极，以向有源块提供完整的VDD电源电压。 小于VDD的待机电压被施加到n沟道晶体管的栅极，以向非活动块提供降低的电源电压。 可以在可编程逻辑器件的运行时间和/或设计时间期间确定非活动块。

    Non-volatile memory array using gate breakdown structures
    3.
    发明授权
    Non-volatile memory array using gate breakdown structures 有权
    使用门击穿结构的非易失性存储器阵列

    公开(公告)号：US06522582B1

    公开(公告)日：2003-02-18

    申请号：US09553571

    申请日：2000-04-19

    申请人： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

    发明人： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

    IPC分类号： G11C1400

    CPC分类号： G11C16/08

    摘要： Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.

    摘要翻译： 描述了用于非易失性存储器件的存储单元结构和相关电路。 可以使用标准CMOS工艺制造电池结构，例如 次0.35微米或次级0.25微米工艺。 优选地，可以使用0.18微米或0.15微米标准CMOS工艺制造电池结构。 有利地，电池结构可以被编程，使得在相似类型的材料之间形成导电路径。 例如，在某些单元结构中，通过施加编程电压来编程单元，以便在p型栅极和p型源极/漏极区域或n型栅极和n型栅极之间形成导电路径 型源极/漏极区域。 以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。 此外，提供了新颖的电荷泵电路，在优选实施例中，它们以“存储器”阵列位于芯片上。 这些电荷泵电路优选地利用用于形成存储器单元结构和相关电路的相同的标准CMOS处理技术来制造。

    Method for over-etching to improve voltage distribution
    4.
    发明授权
    Method for over-etching to improve voltage distribution 失效
    用于过蚀刻以改善电压分布的方法

    公开(公告)号：US6057589A

    公开(公告)日：2000-05-02

    申请号：US61817

    申请日：1998-04-16

    申请人： Kevin T. Look ,  Yakov Karpovich ,  Michael J. Hart

    发明人： Kevin T. Look ,  Yakov Karpovich ,  Michael J. Hart

    IPC分类号： H01L23/525 ,  H01L29/00 ,  H01L21/70

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： An over-etched (OE) antifuse includes a lower electrode, an antifuse layer contacting the lower electrode by an over-etched via, and a second conductive layer formed on the antifuse layer. This over-etched via forms a trench in the lower electrode, wherein in one embodiment the depth of the trench approximates the thickness of the antifuse layer. The trench narrows the programming voltage distribution of the antifuses on the device, irrespective of topology. Because active circuits can be placed underneath the OE antifuses, the present invention dramatically reduces chip size in comparison to conventional devices.

    摘要翻译： 过蚀刻（OE）反熔丝包括下电极，通过过蚀刻通孔与下电极接触的反熔丝层，以及形成在反熔丝层上的第二导电层。 该过蚀刻通孔在下电极中形成沟槽，其中在一个实施例中，沟槽的深度接近反熔丝层的厚度。 沟槽缩小了设备上反熔文件的编程电压分布，而不考虑拓扑结构。 由于有源电路可以放置在OE反熔丝之下，因此与传统的器件相比，本发明显着地减小了芯片的尺寸。

    Method of forming multilayer amorphous silicon antifuse
    5.
    发明授权
    Method of forming multilayer amorphous silicon antifuse 失效
    形成多层非晶硅反熔丝的方法

    公开(公告)号：US5970372A

    公开(公告)日：1999-10-19

    申请号：US1022

    申请日：1997-12-30

    申请人： Michael J. Hart ,  Kevin T. Look ,  Yakov Karpovich

    发明人： Michael J. Hart ,  Kevin T. Look ,  Yakov Karpovich

    IPC分类号： H01L23/525 ,  H01L29/00

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

    摘要翻译： 提供了包括第一和第二导电层以及位于第一和第二导电层之间的反熔丝层的防潮装置。 反熔丝层包括位于两个非晶硅层之间的至少一个氧化物层。 还提供了互连结构和可编程逻辑器件，其包括反熔丝。

    Multilayer amorphous silicon antifuse
    9.
    发明授权
    Multilayer amorphous silicon antifuse 失效
    多层非晶硅反熔丝

    公开(公告)号：US5726484A

    公开(公告)日：1998-03-10

    申请号：US611897

    申请日：1996-03-06

    申请人： Michael J. Hart ,  Kevin T. Look ,  Yakov Karpovich

    发明人： Michael J. Hart ,  Kevin T. Look ,  Yakov Karpovich

    IPC分类号： H01L23/525 ,  H01L29/04 ,  H01L27/10 ,  H01L29/00

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

    摘要翻译： 提供了包括第一和第二导电层以及位于第一和第二导电层之间的反熔丝层的防潮装置。 反熔丝层包括位于两个非晶硅层之间的至少一个氧化物层。 还提供了互连结构和可编程逻辑器件，其包括反熔丝。

    Antifuse structure with increased breakdown at edges
    10.
    发明授权
    Antifuse structure with increased breakdown at edges 失效
    防腐结构边缘增加破裂

    公开(公告)号：US5475253A

    公开(公告)日：1995-12-12

    申请号：US132071

    申请日：1993-10-04

    申请人： Kevin T. Look ,  Evert A. Wolsheimer

    发明人： Kevin T. Look ,  Evert A. Wolsheimer

    IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  H01L29/04 ,  H01L27/02 ,  H01L49/00

    CPC分类号： H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

    摘要： An antifuse is provided which includes a first conductive layer, an antifuse layer formed on the first conductive layer, and a second conductive layer formed on the antifuse layer. A portion of the antifuse layer forms a substantially orthogonal angle with the first conductive layer and the second conductive layer. This "corner" formation of the antifuse enhances the electric field at this location during programming, thereby providing a predictable location for the filament, i.e. the conductive path between the first and second conductive layers. This antifuse provides other advantages including: a relatively low programming voltage, good step coverage for the antifuse layer and the upper conductive layer, a low, stable resistance value, and minimal shearing effects on the filament.

    摘要翻译： 提供一种反熔丝，其包括第一导电层，形成在第一导电层上的反熔丝层，以及形成在反熔丝层上的第二导电层。 反熔丝层的一部分与第一导电层和第二导电层形成大致正交的角度。 反熔丝的这种“角”形成在编程期间增强了该位置处的电场，从而为灯丝提供可预测的位置，即第一和第二导电层之间的导电路径。 该反熔丝提供了其它优点，包括：相对较低的编程电压，反熔丝层和上导电层的良好阶梯覆盖，低稳定的电阻值以及对细丝的最小剪切效应。