公开(公告)号：US07504854B1

公开(公告)日：2009-03-17

申请号：US10783589

申请日：2004-02-20

申请人： Kevin T. Look ,  Michael J. Hart ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

发明人： Kevin T. Look ,  Michael J. Hart ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC分类号： H03K19/173 ,  G11C5/14

CPC分类号： H03K19/1778 ,  G11C5/14 ,  H03K19/17784

摘要： A method of operating a programmable logic device, including the steps of using a full VDD supply voltage to operate one or more active blocks of the programmable logic device, and using a reduced supply voltage (e.g., ½ VDD) to operate one or more inactive blocks of the programmable logic device. The full VDD supply voltage and reduced supply voltage can be provided to the blocks of the programmable logic device through high-voltage n-channel transistors. A boosted voltage, greater than VDD, is applied to the gate of an n-channel transistor to provide the full VDD supply voltage to an active block. A standby voltage, less than VDD, is applied to the gate of an n-channel transistor to provide the reduced supply voltage to an inactive block. The inactive blocks can be determined during run time and/or design time of the programmable logic device.

摘要翻译： 一种操作可编程逻辑器件的方法，包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的一个或多个有效块，以及使用降低的电源电压（例如，½VDD）来操作一个或多个不活动的 可编程逻辑器件的块。 可以通过高电压n沟道晶体管向可编程逻辑器件的块提供完整的VDD电源电压和降低的电源电压。 大于VDD的升压电压被施加到n沟道晶体管的栅极，以向有源块提供完整的VDD电源电压。 小于VDD的待机电压被施加到n沟道晶体管的栅极，以向非活动块提供降低的电源电压。 可以在可编程逻辑器件的运行时间和/或设计时间期间确定非活动块。

公开(公告)号：US08099691B1

公开(公告)日：2012-01-17

申请号：US12491174

申请日：2009-06-24

申请人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

发明人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC分类号： G06F17/50

CPC分类号： H03K19/17784

摘要： A method of operating an integrated circuit (“IC”) is disclosed. The method includes identifying one or more unused or inactive resources of the IC which will not be used in a circuit design or which are inactive during operation of the IC. The method also includes enabling resources of the IC which will be used in the circuit design, and also disabling one or more unused or inactive resources of the IC from one or more power supply terminals in response to configuration values which are stored in memory cells.

摘要翻译： 公开了一种操作集成电路（“IC”）的方法。 该方法包括识别不在电路设计中使用的IC中的一个或多个未使用或非活动资源，或者在IC运行期间不活动的资源。 该方法还包括启用将用于电路设计中的IC的资源，以及响应于存储在存储单元中的配置值，从一个或多个电源端子禁用IC的一个或多个未使用或不活动的资源。

公开(公告)号：US07549139B1

公开(公告)日：2009-06-16

申请号：US10783216

申请日：2004-02-20

申请人： Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

发明人： Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

IPC分类号： G06F17/50 ,  H03K19/00

CPC分类号： H03K19/17784 ,  G11C5/14 ,  H03K3/356173 ,  H03K19/0016 ,  H03K19/17792

摘要： A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.

摘要翻译： 一种操作可编程逻辑器件的方法包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的第一组有源块，并使用降低的电源电压（例如，0.9Vd）来操作第二组 可编程逻辑器件的有源块。 执行时序分析以确定每个活动块中的最大可用时序松弛。 具有较小定时松弛的有源块被分组在第一组中，并且被耦合以接收完整的VDD电源电压。 具有较大定时松弛的有源块被分组在第二组中，并被耦合以接收降低的VDD电源电压。 结果，第二组中的活动块表现出降低的功耗，而不会对可编程逻辑器件的总速度产生不利影响。

公开(公告)号：US07098689B1

公开(公告)日：2006-08-29

申请号：US10666669

申请日：2003-09-19

申请人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

发明人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC分类号： H03K19/094 ,  H03K19/177 ,  G05F1/10 ,  G11C5/14

CPC分类号： H03K19/17784

摘要： A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

公开(公告)号：US07581124B1

公开(公告)日：2009-08-25

申请号：US11326542

申请日：2006-01-04

申请人： Neil G. Jacobson ,  Matthew T. Murphy ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

发明人： Neil G. Jacobson ,  Matthew T. Murphy ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC分类号： G06F1/22

CPC分类号： G11C5/14 ,  G11C5/148 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0401 ,  H03K19/17784

摘要： A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.

摘要翻译： PLD包括多个逻辑块，测试电路和测试引脚组。 逻辑块耦合到选通电路，门电路响应于控制信号选择性地调整块的工作电压。 在PLD的操作期间，响应于通过测试引脚设置到PLD的外部产生的信号来更新控制信号，并使用测试电路将其传送到逻辑块。

公开(公告)号：US07562332B1

公开(公告)日：2009-07-14

申请号：US11502939

申请日：2006-08-11

申请人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

发明人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC分类号： G06F17/50

CPC分类号： H03K19/17784

摘要： A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

摘要翻译： 一种操作可编程逻辑器件的方法，包括以下步骤：使可编程逻辑器件的资源在由可编程逻辑器件实现的电路设计中使用，以及禁用未被使用的可编程逻辑器件的未使用或不活动资源 电路设计。 禁用的步骤可以包括从一个或多个电源端子去耦合未使用或不活动的资源。 或者，禁用步骤可以包括调节施加到未使用或不活动资源的电源电压。 可以响应于由可编程逻辑器件存储的配置数据位和/或响应于用户控制的信号来执行禁用步骤。 可以在可编程逻辑器件的设计时间和/或运行时间期间启动禁用步骤。

公开(公告)号：US07046071B1

公开(公告)日：2006-05-16

申请号：US10633727

申请日：2003-08-04

申请人： Robert O. Conn ,  Kameswara K. Rao

发明人： Robert O. Conn ,  Kameswara K. Rao

IPC分类号： H03K17/62 ,  H03K17/693

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/1778 ,  H03K19/17796

摘要： A series capacitor coupling (SCC) structure is controllable to capacitively couple a data input lead of the SCC structure to an output lead of the SCC, or to de-couple the data input lead from the data output lead. An SCC is controlled by a control bit stored in an associated memory cell. A multiplexer is fashioned out of a plurality of such SCC structures such that the edges of a digital signal received on a selected one of a plurality of multiplexer data input leads is coupled through the SCC structures onto an intervening node. The edges of the digital signal on the intervening node are then latched to recreate the incoming digital signal and the latched signal is output onto a multiplexer data output lead. The multiplexer is very fast and has a low leakage current in comparison to conventional transmission gate multiplexers used in programmable logic devices.

摘要翻译： 串联电容耦合（SCC）结构是可控制的，以将SCC结构的数据输入引线电容耦合到SCC的输出引线，或者从数据输出引线去耦合数据输入引线。 SCC由存储在关联的存储单元中的控制位控制。 从多个这样的SCC结构中形成多路复用器，使得在多个多路复用器数据输入引线中的选定的一个上接收的数字信号的边缘通过SCC结构耦合到中间节点上。 然后中断节点上的数字信号的边沿被锁存以重建输入的数字信号，并且锁存的信号被输出到多路复用器数据输出引线上。 与可编程逻辑器件中使用的常规传输栅极复用器相比，多路复用器非常快，具有低漏电流。

公开(公告)号：US08129834B2

公开(公告)日：2012-03-06

申请号：US12321833

申请日：2009-01-26

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H01L23/482 ,  H01L23/49 ,  H01L23/492 ,  H01L23/367

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination.

摘要翻译： 多个FPGA管芯设置在半导体衬底上。 为了提供多个FPGA芯片所需的巨大功率，功率从位于半导体衬底另一侧的厚金属层和大的整体金属结构垂直地穿过半导体衬底。 由于半导体衬底与与衬底接触的金属层具有不同的热线性膨胀系数，所以当结构经受温度变化时，可能发生分层。 为了防止与半导体衬底连接并与整体金属结构电接触的金属层的分层，整体金属结构被制成具有一定数量的柱部分。 在温度变化期间，整体金属结构的后部相对于连接到半导体衬底的金属层弯曲和滑动，并且防止否则会引起分层的线性应力。

公开(公告)号：US20110239456A1

公开(公告)日：2011-10-06

申请号：US12798132

申请日：2010-03-30

申请人： Robert O. Conn ,  Daniel S. Stevenson

发明人： Robert O. Conn ,  Daniel S. Stevenson

IPC分类号： H05K3/34

CPC分类号： H01L24/81 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05147 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13562 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/8114 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2203/047 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49169 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.

摘要翻译： 低温焊球连接两个具有不同的线性热膨胀系数的结构。 制造集成电路以加热该器件，使得低温接合球熔化。 熔化后，粘结球固化，并且使粘合球固化的装置进行操作。 在一个示例中，两个结构之一是半导体衬底，而另一个结构是印刷电路板。 集成电路是安装到半导体衬底的裸片。 结合球包括至少5％的铟，并且集成电路是装载有位流的FPGA。 位流配置FPGA，使得FPGA具有增加的功率耗散，其熔化了球。 熔化后，将第二位流装载到FPGA中，并使用第二位流以正常用户模式操作FPGA。

公开(公告)号：US07709966B2

公开(公告)日：2010-05-04

申请号：US11952495

申请日：2007-12-07

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/147 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15165 ,  H01L2924/157 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

摘要： An electronic package and methods by which the package reduces thermal fatigue failure of conductors in the electronic package. The electronic package includes a carrier substrate having first and second surfaces and a plurality of anchor vias having a via material extending from the first surface toward the second surface. The electronic package includes a first conducting layer having a length and a width extending laterally in two dimensions across a major part of the first surface of the carrier substrate. The anchor vias have plural attachments along the length and the width of the first conducting layer to secure the first conducting layer to the carrier substrate.

摘要翻译： 电子封装和封装的方法减少电子封装中导体的热疲劳失效。 电子封装包括具有第一和第二表面的载体基板和具有从第一表面向第二表面延伸的通孔材料的多个锚定通孔。 电子封装包括第一导电层，第一导电层的长度和宽度横向延伸穿过载体衬底的第一表面的主要部分。 锚定通孔沿着第一导电层的长度和宽度具有多个附着物，以将第一导电层固定到载体基底。