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    METHOD AND DEVICES FOR TIME TRANSFER USING END-TO-END TRANSPARENT CLOCKS
    3.
    发明申请
    METHOD AND DEVICES FOR TIME TRANSFER USING END-TO-END TRANSPARENT CLOCKS 有权
    使用端到端透明时钟传输时间的方法和设备

    公开(公告)号：US20160170440A1

    公开(公告)日：2016-06-16

    申请号：US14566990

    申请日：2014-12-11

    申请人： Khalifa University of Science, Technology, and Research ,  British Telecommunications plc ,  Emirates Telecommunications Corporation

    发明人： James Aweya

    IPC分类号： G06F1/12 ,  H04L29/08

    CPC分类号： G06F1/12 ,  G06F1/10 ,  H04L69/28

    摘要： This invention relates to methods and devices for time transfer. The invention has particular application in the alignment of slave clocks to a master clock and dealing with packet delay variations. In embodiments of the invention, the slave clock uses the residence times measured by end-to-end transparent clocks to compensate for clock synchronization errors that arise due to variability in message transfer delays. Embodiments provide a simple linear approximation technique and a Kalman filter-based technique for estimating offset and skew of the slave clock.

    摘要翻译： 本发明涉及时间传递的方法和装置。 本发明特别适用于将从时钟对准主时钟并处理分组延迟变化。 在本发明的实施例中，从时钟使用由端对端透明时钟测量的停留时间来补偿由于消息传送延迟的变化而产生的时钟同步误差。 实施例提供了简单的线性近似技术和用于估计从时钟的偏移和偏移的基于卡尔曼滤波器的技术。

    METHOD AND DEVICES FOR TIME TRANSFER USING PEER-TO-PEER TRANSPARENT CLOCKS
    4.
    发明申请
    METHOD AND DEVICES FOR TIME TRANSFER USING PEER-TO-PEER TRANSPARENT CLOCKS 有权
    使用对等透明时钟传输时间的方法和装置

    公开(公告)号：US20160170439A1

    公开(公告)日：2016-06-16

    申请号：US14566951

    申请日：2014-12-11

    申请人： Khalifa University of Science, Technology, and Research ,  British Telecommunications plc ,  Emirates Telecommunications Corporation

    发明人： James Aweya

    IPC分类号： G06F1/12 ,  H04L29/08

    CPC分类号： G06F1/12 ,  G06F1/10 ,  H04L69/28

    摘要： This invention relates to methods and devices for time synchronization. The invention has particular application in the alignment of slave clocks to a master clock and in dealing with packet delay variation and dynamic asymmetries in the network links between them. In embodiments of the invention, the slave clock uses the peer link delay and residence times measured by peer-to-peer transparent clocks to compensate for clock synchronization errors that arise due to variability in message transfer delays. Embodiments provide a simple linear approximation technique and a Kalman filter-based technique for estimating offset and skew of the slave clock.

    摘要翻译： 本发明涉及时间同步的方法和装置。 本发明在从属时钟对主时钟和处理它们之间的网络链路中的分组延迟变化和动态不对称性方面具有特别的应用。 在本发明的实施例中，从时钟使用由对等透明时钟测量的对等链路延迟和驻留时间来补偿由于消息传送延迟的变化而产生的时钟同步错误。 实施例提供了简单的线性近似技术和用于估计从时钟的偏移和偏移的基于卡尔曼滤波器的技术。

    METHODS AND DEVICES FOR BIAS ESTIMATION AND CORRECTION
    5.
    发明申请
    METHODS AND DEVICES FOR BIAS ESTIMATION AND CORRECTION 有权
    用于偏差估计和校正的方法和装置

    公开(公告)号：US20160069676A1

    公开(公告)日：2016-03-10

    申请号：US14477191

    申请日：2014-09-04

    申请人： Khalifa University of Science, Technology, and Research ,  British Telecommunications plc ,  Emirates Telecommunications Corporation

    发明人： Nayef Alsindi ,  James Aweya ,  Zdenek Chaloupka

    IPC分类号： G01B21/16 ,  G01S19/00

    CPC分类号： G01S19/00 ,  G01S5/0215 ,  G01S19/22

    摘要： This invention relates to methods and devices for bias estimation and correction, particularly for time-of-arrival (TOA) based wireless geolocation systems. Multipath and non-line-of-sight (NLOS) biases can cause distance estimation errors in the range of tens-hundreds of meters and is particularly problematic in urban and indoor environments. The behaviour of the biases dynamically changes depending on the clutter and/or obstructions between the base station and the mobile device. Aspects of the present invention provide practical real-time bias estimation and correction techniques for TOA-based systems and are based on inferring and estimating the biases from dynamic time differential measurements. The techniques can operate in real-time and involve simple calculations.

    摘要翻译： 本发明涉及用于偏差估计和校正的方法和装置，特别是用于基于到达时间（TOA）的无线地理定位系统。 多路径和非视距（NLOS）偏差可能导致距离估计误差在数百米范围内，并且在城市和室内环境中尤其成问题。 偏移的动作根据基站和移动设备之间的杂波和/或障碍物动态地变化。 本发明的各方面为基于TOA的系统提供实用的实时偏差估计和校正技术，并且基于从动态时间差分测量推断和估计偏差。 这些技术可以实时操作，并且涉及简单的计算。

    Method and devices for frequency distribution
    8.
    发明授权
    Method and devices for frequency distribution 有权
    频率分配方法和装置

    公开(公告)号：US09112631B2

    公开(公告)日：2015-08-18

    申请号：US14023815

    申请日：2013-09-11

    申请人： Khalifa University of Science, Technology, and Research ,  British Telecommunications plc ,  Emirates Telecommunications Corporation

    发明人： James Aweya ,  Nayef Al Sindi ,  Saeed Al-Zubaidi

    IPC分类号： H04J3/06

    CPC分类号： H04J3/0682 ,  H04J3/0664 ,  H04J3/0667 ,  H04J3/0673 ,  H04J3/0697

    摘要： This invention relates to methods and devices for frequency distribution based on, for example, the IEEE 1588 Precision Time Protocol (PTP). Packet delay variation (PDV) is a direct contributor to the noise in the recovered clock and various techniques have been proposed to mitigate its effects. Embodiments of the invention provide a mechanism to directly measure and remove PDV effects in the clock recovery mechanism at a slave clock. One particular embodiment provides a clock recovery mechanism including a phase-locked loop (PLL) with a PDV compensation feature built-in. An aim of the invention is to enable a slave clock to recover the master clock to a higher quality as if the communication path between master and slave is free of PDV. This technique may allow a packet network to provide clock synchronization services to the same level as time division multiplexing (TDM) networks and Global Positioning System (GPS).

    摘要翻译： 本发明涉及基于例如IEEE 1588精确时间协议（PTP）的用于频率分布的方法和装置。 分组延迟变化（PDV）是恢复时钟中的噪声的直接贡献者，并且已经提出了各种技术来减轻其影响。 本发明的实施例提供了一种在从时钟处直接测量和去除时钟恢复机制中的PDV效应的机制。 一个具体实施例提供了一种时钟恢复机制，其包括具有内置PDV补偿特征的锁相环（PLL）。 本发明的目的是使从时钟将主时钟恢复到更高的质量，就好像主机和从机之间的通信路径没有PDV一样。 该技术可以允许分组网络提供与时分复用（TDM）网络和全球定位系统（GPS）相同级别的时钟同步服务。

    METHOD AND DEVICES FOR SYNCHRONIZATION USING LINEAR PROGRAMMING
    9.
    发明申请
    METHOD AND DEVICES FOR SYNCHRONIZATION USING LINEAR PROGRAMMING 有权
    使用线性编程进行同步的方法和设备

    公开(公告)号：US20150163000A1

    公开(公告)日：2015-06-11

    申请号：US14100345

    申请日：2013-12-09

    申请人： Khalifa University of Science, Technology, and Research ,  Emirates Telecommunications Corporation ,  British Telecommunications plc

    发明人： James Aweya

    IPC分类号： H04J3/06 ,  H04L7/033

    CPC分类号： H04J3/0602 ,  H04J3/0667 ,  H04L7/033

    摘要： This invention relates to methods and devices for synchronization using linear programming, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a two-dimensional linear programming technique for estimating clock offset and skew, particularly from two-way exchange of timing messages between a master and a slave device. Some embodiments include a skew and offset adjustable free-running counter for regenerating the master time and frequency at the slave device.

    摘要翻译： 本发明涉及使用线性规划进行同步的方法和装置，特别是使用例如IEEE 1588精确时间协议（PTP）的分组网络。 定时协议消息暴露在网络中的伪影，例如分组延迟变化（PDV）或分组丢失。 本发明的实施例提供了一种用于估计时钟偏移和偏移的二维线性规划技术，特别是从主设备和从设备之间的定时消息的双向交换。 一些实施例包括用于在从设备处再生主时间和频率的偏斜和偏移可调自由运行计数器。

    METHOD AND DEVICES FOR TIME AND FREQUENCY SYNCHRONIZATION USING A PHASE LOCKED LOOP
    10.
    发明申请
    METHOD AND DEVICES FOR TIME AND FREQUENCY SYNCHRONIZATION USING A PHASE LOCKED LOOP 有权
    使用相位锁定环路的时间和频率同步的方法和设备

    公开(公告)号：US20150092797A1

    公开(公告)日：2015-04-02

    申请号：US14044075

    申请日：2013-10-02

    申请人： Khalifa University of Science, Technology, and Research ,  Emirates Telecommunications Corporation ,  British Telecommunications plc

    发明人： James Aweya

    IPC分类号： H04J3/06

    CPC分类号： H03L7/1976 ,  H03L2207/50 ,  H04J3/0667 ,  H04J3/0697

    摘要： This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.

    摘要翻译： 本发明涉及用于时间和频率同步的方法和装置，特别是涉及使用例如IEEE 1588精确时间协议（PTP）的分组网络。 定时协议消息暴露在网络中的伪影，例如分组延迟变化（PDV）或分组丢失。 本发明的实施例提供了一种基于直接数字合成的数字锁相环（DPLL），以提供在从机（时间客户机）上使用的时间和频率信号。 还提供了该DPLL与用于时钟偏移和偏移估计的递归最小二乘机制的示例。