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1.发明申请PRECISE DELAY ALIGNMENT BETWEEN AMPLITUDE AND PHASE/FREQUENCY MODULATION PATHS IN A DIGITAL POLAR TRANSMITTER 有权数字极性放大器中的幅度和相位/频率调制方式之间的精确延迟对准公开(公告)号：US20070189417A1
公开(公告)日：2007-08-16
申请号：US11675565
申请日：2007-02-15
CPC分类号： H04L27/368 , H03C5/00 , H04L7/0029 , H04L7/0041 , H04L7/005 , H04L7/0079 , H04L7/02
摘要： A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.
摘要翻译： 数字极性发射机的幅度和相位/频率调制路径之间的延迟对准的新型装置和方法。 本发明提供了一种全数字延迟对准机制，其通过考虑发射机的数字电路模块中的处理延迟以及通过使用分布在几个时钟域上的可编程延迟元件来实现比纳秒对准更好的方法。 分接延迟线补偿模拟元件（如DCO，分频器，四通道开关，缓冲器，电平移位器和数字预功率放大器（DPA））中的传播和稳定延迟。 提供了一种信号相关机制，其中来自要匹配的幅度和相位/频率调制路径的数据首先被内插，然后进行交叉相关，以获得比时钟域更好的比较。 在发射机的ADPLL部分内，使用多个时钟域，抽头延迟线和时钟调整电路来证明ADPLL中的参考点和直接点注入点的精确对准。
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2.发明授权Precise delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter 有权数字极化发射机中幅度和相位/频率调制路径之间的精确延迟对准公开(公告)号：US07817747B2
公开(公告)日：2010-10-19
申请号：US11675565
申请日：2007-02-15
IPC分类号： H04L27/36
CPC分类号： H04L27/368 , H03C5/00 , H04L7/0029 , H04L7/0041 , H04L7/005 , H04L7/0079 , H04L7/02
摘要： A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.
摘要翻译： 数字极性发射机的幅度和相位/频率调制路径之间的延迟对准的新型装置和方法。 本发明提供了一种全数字延迟对准机构，其通过考虑发射机的数字电路模块中的处理延迟以及通过使用分布在几个时钟域上的可编程延迟元件来实现比纳秒对准更好的方法。 分接延迟线补偿模拟元件（如DCO，分频器，四通道开关，缓冲器，电平移位器和数字预功率放大器（DPA））中的传播和稳定延迟。 提供了一种信号相关机制，其中来自要匹配的幅度和相位/频率调制路径的数据首先被内插，然后进行交叉相关，以获得比时钟域更好的比较。 在发射机的ADPLL部分内，使用多个时钟域，抽头延迟线和时钟调整电路来证明ADPLL中的参考点和直接点注入点的精确对准。
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3.发明授权Linearization and calibration predistortion of a digitally controlled power amplifier 有权数字控制功率放大器的线性化和校准预失真公开(公告)号：US09020454B2
公开(公告)日：2015-04-28
申请号：US13481450
申请日：2012-05-25
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译： 用于执行预失真校准以补偿DPA和PA电路中的非线性的数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的装置和方法。 预失真查询表（LUT）存储在被输入到数字 - 频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。 在半双工操作期间TX突发期间通常不工作的片上接收器解调RF PA输出并使用数字I / Q RX输出来执行TX预失真表的校准。 将RF输出信号的样本提供给接收器链。 当PA（DPA）代码正在增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值， 可以计算预失真表。
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公开(公告)号：US20070190952A1
公开(公告)日：2007-08-16
申请号：US11675582
申请日：2007-02-15
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp. While the digitally-controlled PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译： 一种数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的新型装置和方法。 该机制可用于执行预失真校准，以补偿DPA和PA电路中的非线性。 预失真查询表（LUT）存储在被输入到数字到频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。 本发明的机制利用在半双工操作期间的TX突发期间通常不工作的片上接收机来解调RF PA输出并使用数字I / Q RX输出来执行TX的校准 预失真表。 受控RF耦合用于向接收机链提供RF输出信号的采样。 预失真LUT的内容通常在PA上电或下降斜坡期间更新。 当数字控制的PA（DPA）码增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值， 可以计算对预失真表的更新。
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公开(公告)号：US20120263256A1
公开(公告)日：2012-10-18
申请号：US13481450
申请日：2012-05-25
IPC分类号： H04L25/49
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译： 用于执行预失真校准以补偿DPA和PA电路中的非线性的数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的装置和方法。 预失真查询表（LUT）存储在被输入到数字 - 频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。 在半双工操作期间TX突发期间通常不工作的片上接收器解调RF PA输出并使用数字I / Q RX输出来执行TX预失真表的校准。 将RF输出信号的样本提供给接收器链。 当PA（DPA）代码正在增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值， 可以计算预失真表。
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公开(公告)号：US08195103B2
公开(公告)日：2012-06-05
申请号：US11675582
申请日：2007-02-15
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp. While the digitally-controlled PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译： 一种数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的新型装置和方法。 该机制可用于执行预失真校准，以补偿DPA和PA电路中的非线性。 预失真查询表（LUT）存储在被输入到数字到频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。 本发明的机制利用在半双工操作期间TX突发期间通常不活动的片上接收机来解调RF PA输出并使用数字I / Q RX输出来执行TX的校准 预失真表。 受控RF耦合用于向接收机链提供RF输出信号的采样。 预失真LUT的内容通常在PA上电或下降斜坡期间更新。 当数字控制的PA（DPA）码增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值， 可以计算对预失真表的更新。
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7.发明申请PREDISTORTION MECHANISM FOR COMPENSATION OF TRANSISTOR SIZE MISMATCH IN A DIGITAL POWER AMPLIFIER 审中-公开用于补偿数字功率放大器中晶体管尺寸误差的预测机制公开(公告)号：US20100188148A1
公开(公告)日：2010-07-29
申请号：US12359613
申请日：2009-01-26
IPC分类号： H03F1/26
CPC分类号： H03F1/3247 , H03F1/30
摘要： A novel and useful apparatus for and method of predistortion compensation of device (e.g., transistor) mismatch in a digital power amplifier (DPA). The device mismatch predistortion mechanism of the present invention addresses the problem of matching between two types of binary weighted transistors, whereby mismatched transistors cause degradation in wideband noise. The invention provides a digital predistortion mechanism which functions to pre-distort the mismatch ratio based on a data table calculated a priori enabling a polar transmitter to meet output spectrum and error vector magnitude (EVM) requirements of the particular modern wideband wireless standard, such as GSM, 3G WCDMA, etc.
摘要翻译： 一种用于数字功率放大器（DPA）中的器件（例如，晶体管）失配的预失真补偿的新颖有用的装置和方法。 本发明的器件失配预失真机制解决了两种二进制加权晶体管之间的匹配问题，由此失配的晶体管导致宽带噪声的降低。 本发明提供了一种数字预失真机制，其用于基于先前计算的数据表来预失真失配比，使得极性发射机能够满足特定现代宽带无线标准的输出频谱和误差矢量幅度（EVM）要求，例如 GSM，3G WCDMA等
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8.发明申请UPSAMPLING/INTERPOLATION AND TIME ALIGNMENT MECHANISM UTILIZING INJECTION OF HIGH FREQUENCY NOISE 审中-公开使用高频噪声的注射/插入和时间校准机制公开(公告)号：US20100135368A1
公开(公告)日：2010-06-03
申请号：US12326781
申请日：2008-12-02
CPC分类号： H04L27/38 , H03H17/0671 , H04L27/3863 , H04L27/3872 , H04L27/3881 , H04L27/389
摘要： A novel and useful apparatus for and method of upsampling/interpolating a discrete-time input sample stream with time alignment utilizing the addition of randomized high frequency noise. The upsampling mechanism is an effective implementation of a second order interpolator that eliminates the need for a conventional filter as the filtering action is effectively built into the mechanism. The upsampling mechanism takes the derivative of the discrete-time input sample stream, thereby effectively providing another order of interpolation over a conventional interpolator. Before outputting the interpolated signal, an integrator takes the integral of the interpolated samples. Any processing performed between the derivative and integrator blocks effectively provides an additional order of interpolation. High frequency noise (i.e. dithering) is added to the differentiated samples in order to eliminate the spectral regrowth spurs that would otherwise appear in the output after rounding. Delay alignment is performed on the differentiated samples in order to time align both phase/frequency and amplitude samples that are processed on different paths.
摘要翻译： 一种新颖有用的装置和方法，其利用随机化的高频噪声的添加，利用时间对准对离散时间输入样本流进行上采样/内插。 上采样机制是二阶插值器的有效实现，其消除了对传统滤波器的需要，因为滤波动作被有效地内置到机构中。 上采样机制采用离散时间输入采样流的导数，从而有效地为常规内插器提供了另一个内插次序。 在输出内插信号之前，积分器取内插样本的积分。 在导数和积分器块之间执行的任何处理有效地提供了一个额外的内插次序。 将高频噪声（即抖动）加到差分采样中，以消除在舍入后将出现在输出中的频谱再生马刺。 对差分样本执行延迟对齐，以便对在不同路径上处理的相位/频率和振幅样本进行时间对齐。
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9.发明授权Transmitter for wireless applications incorporation spectral emission shaping sigma delta modulator 有权用于无线应用的发射机并入光谱发射整形Σ-Δ调制器公开(公告)号：US07787563B2
公开(公告)日：2010-08-31
申请号：US11297524
申请日：2005-12-07
IPC分类号： H04L25/49
CPC分类号： H03M7/3017 , H03M7/3022 , H03M7/3042
摘要： A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.
摘要翻译： 一种采用具有噪声传递函数的Σ-Δ调制器的发射机，其适于在至少一个感兴趣的频带之外移位量化噪声。 提出了一种用于合成单环Σ-Δ调制器中的控制器的技术，使得噪声传递函数可以从满足某些条件的函数族中任意选择。 使用新颖的调制器设计技术，支持极坐标和笛卡尔（即正交）发射机结构。 呈现采用极性发射调制的发射机，其对数字控制的功率放大器的频谱发射进行整形，使得它们在一个或多个期望的频带中显着且充分衰减。 类似地，呈现采用笛卡尔发射调制的发射机，其对混合功率放大器的频谱发射进行整形，使得它们在一个或多个期望的频带中显着且充分衰减。
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10.发明授权Negative contributive offset compensation in a transmit buffer utilizing inverse clocking 有权使用反向时钟的发送缓冲器中的负贡献偏移补偿公开(公告)号：US07405685B2
公开(公告)日：2008-07-29
申请号：US11178993
申请日：2005-07-11
IPC分类号： H03M3/00
CPC分类号： H03F1/0205 , H03F1/3241 , H03F2200/331 , H03F2200/375 , H03M3/356 , H03M3/50 , H03M7/3026 , H03M7/3037 , H04L27/368
摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
摘要翻译： 一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。 来自Σ-Δ调制器的正输出的处理方式与负输出不同。 与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。 时钟的非反相版本与正输出一起使用，反向时钟与负输出一起使用。 使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。 结果是具有零偏移的偏移补偿RF输出信号。
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