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    Trench isolation type semiconductor device which prevents a recess from being formed in a field region and method of fabricating the same
    1.
    发明授权
    Trench isolation type semiconductor device which prevents a recess from being formed in a field region and method of fabricating the same 有权
    防止在场区域形成凹部的沟槽隔离型半导体器件及其制造方法

    公开(公告)号：US07795110B2

    公开(公告)日：2010-09-14

    申请号：US12070808

    申请日：2008-02-21

    申请人： Ki-seog Youn ,  Jong-hyon Ahn ,  Deok-hyung Lee ,  Sung-gun Kang ,  Kong-soo Cheong

    发明人： Ki-seog Youn ,  Jong-hyon Ahn ,  Deok-hyung Lee ,  Sung-gun Kang ,  Kong-soo Cheong

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224

    摘要： A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.

    摘要翻译： 提供其中防止在场区域中形成凹部的沟槽隔离型半导体器件及其制造方法。 沟槽隔离型半导体器件包括由有源区和场区定义的半导体衬底，在场区中形成的沟槽，沿着沟内部保形地形成的氧化物层，沿着氧化物层保形地形成的衬层， 形成在包括氧化物层和衬垫层的沟槽内的场绝缘层，以及形成在场绝缘层上的场保护层，使得半导体衬底上不发生阶差。

    Trench isolation type semiconductor device which prevents a recess from being formed in a field region
    2.
    发明授权
    Trench isolation type semiconductor device which prevents a recess from being formed in a field region 有权
    沟槽隔离型半导体器件防止在场区域中形成凹陷

    公开(公告)号：US07358588B2

    公开(公告)日：2008-04-15

    申请号：US11301510

    申请日：2005-12-13

    申请人： Ki-seog Youn ,  Jong-hyon Ahn ,  Deok-hyung Lee ,  Sung-gun Kang ,  Kong-soo Cheong

    发明人： Ki-seog Youn ,  Jong-hyon Ahn ,  Deok-hyung Lee ,  Sung-gun Kang ,  Kong-soo Cheong

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76224

    摘要： A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.

    摘要翻译： 提供其中防止在场区域中形成凹部的沟槽隔离型半导体器件及其制造方法。 沟槽隔离型半导体器件包括由有源区和场区定义的半导体衬底，在场区中形成的沟槽，沿着沟内部保形地形成的氧化物层，沿着氧化物层保形地形成的衬层， 形成在包括氧化物层和衬垫层的沟槽内的场绝缘层，以及形成在场绝缘层上的场保护层，使得半导体衬底上不发生阶差。

    Trench isolation type semiconductor device and method of fabricating the same
    3.
    发明申请
    Trench isolation type semiconductor device and method of fabricating the same 有权
    沟槽隔离型半导体器件及其制造方法

    公开(公告)号：US20060128114A1

    公开(公告)日：2006-06-15

    申请号：US11301510

    申请日：2005-12-13

    申请人： Ki-seog Youn ,  Jong-hyon Ahn ,  Deok-hyung Lee ,  Sung-gun Kang ,  Kong-soo Cheong

    发明人： Ki-seog Youn ,  Jong-hyon Ahn ,  Deok-hyung Lee ,  Sung-gun Kang ,  Kong-soo Cheong

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224

    摘要： A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.

    摘要翻译： 提供其中防止在场区域中形成凹部的沟槽隔离型半导体器件及其制造方法。 沟槽隔离型半导体器件包括由有源区和场区定义的半导体衬底，在场区中形成的沟槽，沿着沟内部保形地形成的氧化物层，沿着氧化物层保形地形成的衬层， 形成在包括氧化物层和衬垫层的沟槽内的场绝缘层，以及形成在场绝缘层上的场保护层，使得半导体衬底上不发生阶差。

    Semiconductor memory devices having vertical channel transistors and related methods
    9.
    发明授权
    Semiconductor memory devices having vertical channel transistors and related methods 有权
    具有垂直沟道晶体管的半导体存储器件及相关方法

    公开(公告)号：US08008698B2

    公开(公告)日：2011-08-30

    申请号：US12198266

    申请日：2008-08-26

    申请人： Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

    发明人： Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10894 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885

    摘要： A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.

    摘要翻译： 半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。 柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。 栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。 此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。 接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。 还讨论了相关方法。

    Methods for fabricating DRAM semiconductor devices including silicon epitaxial and metal silicide layers
    10.
    发明授权
    Methods for fabricating DRAM semiconductor devices including silicon epitaxial and metal silicide layers 失效
    制造包括硅外延和金属硅化物层的DRAM半导体器件的方法

    公开(公告)号：US07579249B2

    公开(公告)日：2009-08-25

    申请号：US11688554

    申请日：2007-03-20

    申请人： Chul-sung Kim ,  Byeong-chan Lee ,  Jong-ryeol Yoo ,  Si-young Choi ,  Deok-hyung Lee

    发明人： Chul-sung Kim ,  Byeong-chan Lee ,  Jong-ryeol Yoo ,  Si-young Choi ,  Deok-hyung Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10894 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

    摘要： Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.

    摘要翻译： 提供了DRAM半导体器件和用于制造DRAM半导体器件的方法。 该方法使用选择性外延生长（SEG）在单元区域的源极/漏极区域和外围电路区域上形成硅外延层，从而形成凸起的有源区域。 此外，在DRAM半导体器件中，在电池区域的源极/漏极区域中的硅外延层上形成金属硅化物层和金属焊盘。 通过这样做，DRAM器件能够形成源极/漏极区域作为浅结区域，从而减少泄漏电流的发生并降低与源极/漏极区域的接触电阻。