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1.发明授权Integrated circuit devices having buried insulation layers and methods of forming the same 失效具有掩埋绝缘层的集成电路器件及其形成方法公开(公告)号：US07081391B2
公开(公告)日：2006-07-25
申请号：US10722193
申请日：2003-11-26
申请人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
发明人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823481 , H01L27/10888
摘要： An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.
摘要翻译： 集成电路器件包括形成在集成电路器件的有源区上的栅电极和与有源区相邻的场隔离层。 源极区域和漏极区域在栅电极的交替侧上的有源区域中。 至少一个掩埋绝缘层位于漏极区域或源极区域之下。
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2.发明申请Integrated circuit devices having buried insulation layers and methods of forming the same 失效具有掩埋绝缘层的集成电路器件及其形成方法公开(公告)号：US20050179073A1
公开(公告)日：2005-08-18
申请号：US10722193
申请日：2003-11-26
申请人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
发明人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
IPC分类号： H01L21/8234 , H01L21/8242 , H01L29/76
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823481 , H01L27/10888
摘要： An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.
摘要翻译： 集成电路器件包括形成在集成电路器件的有源区上的栅电极和与有源区相邻的场隔离层。 源极区域和漏极区域在栅电极的交替侧上的有源区域中。 至少一个掩埋绝缘层位于漏极区域或源极区域之下。
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3.发明申请公开(公告)号：US20060226455A1
公开(公告)日：2006-10-12
申请号：US11450725
申请日：2006-06-09
申请人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
发明人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823481 , H01L27/10888
摘要： An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.
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4.发明授权Methods of forming integrated circuits with thermal oxide layers on side walls of gate electrodes wherein the source and drain are higher than the gate electrode 有权在栅电极的侧壁上形成具有热氧化层的集成电路的方法，其中源极和漏极高于栅电极公开(公告)号：US06890823B2
公开(公告)日：2005-05-10
申请号：US10426562
申请日：2003-04-30
IPC分类号： H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/76889 , H01L21/823425 , H01L21/823443 , H01L21/823468 , H01L29/6656
摘要： Methods of forming thermal oxide layers on a side wall of gate electrodes are disclosed. In particular, thermal oxide layers can be formed on a side wall of a gate electrode by forming a gate electrode on an integrated circuit substrate and forming a thermal oxide layer on a side wall of the gate electrode using a thermal oxidation process. A silicide layer can be formed on the gate electrode after the formation of the thermal oxide layer.
摘要翻译： 公开了在栅电极的侧壁上形成热氧化层的方法。 特别地，可以通过在集成电路基板上形成栅电极并使用热氧化工艺在栅电极的侧壁上形成热氧化层，在栅电极的侧壁上形成热氧化物层。 在形成热氧化物层之后，可以在栅电极上形成硅化物层。
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5.发明授权Methods for fabricating DRAM semiconductor devices including silicon epitaxial and metal silicide layers 失效制造包括硅外延和金属硅化物层的DRAM半导体器件的方法公开(公告)号：US07579249B2
公开(公告)日：2009-08-25
申请号：US11688554
申请日：2007-03-20
IPC分类号： H01L21/336
CPC分类号： H01L27/10894 , H01L27/10855 , H01L27/10873 , H01L27/10888
摘要： Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.
摘要翻译： 提供了DRAM半导体器件和用于制造DRAM半导体器件的方法。 该方法使用选择性外延生长（SEG）在单元区域的源极/漏极区域和外围电路区域上形成硅外延层，从而形成凸起的有源区域。 此外，在DRAM半导体器件中，在电池区域的源极/漏极区域中的硅外延层上形成金属硅化物层和金属焊盘。 通过这样做，DRAM器件能够形成源极/漏极区域作为浅结区域，从而减少泄漏电流的发生并降低与源极/漏极区域的接触电阻。
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6.发明申请METHODS FOR FABRICATING DRAM SEMICONDUCTOR DEVICES INCLUDING SILICON EPITAXIAL AND METAL SILICIDE LAYERS 失效用于制造包含硅外延和金属硅化物层的DRAM半导体器件的方法公开(公告)号：US20070178642A1
公开(公告)日：2007-08-02
申请号：US11688554
申请日：2007-03-20
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/331 , H01L21/20
CPC分类号： H01L27/10894 , H01L27/10855 , H01L27/10873 , H01L27/10888
摘要： Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.
摘要翻译： 提供了DRAM半导体器件和用于制造DRAM半导体器件的方法。 该方法使用选择性外延生长（SEG）在单元区域的源极/漏极区域和外围电路区域上形成硅外延层，从而形成凸起的有源区域。 此外，在DRAM半导体器件中，在电池区域的源极/漏极区域中的硅外延层上形成金属硅化物层和金属焊盘。 通过这样做，DRAM器件能够形成源极/漏极区域作为浅结区域，从而减少泄漏电流的发生并降低与源极/漏极区域的接触电阻。
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7.发明授权Semiconductor memory devices having vertical channel transistors and related methods 有权具有垂直沟道晶体管的半导体存储器件及相关方法公开(公告)号：US08008698B2
公开(公告)日：2011-08-30
申请号：US12198266
申请日：2008-08-26
申请人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
发明人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/0207 , H01L27/10876 , H01L27/10882 , H01L27/10885
摘要： A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.
摘要翻译： 半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。 柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。 栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。 此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。 接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。 还讨论了相关方法。
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8.发明申请Semiconductor Memory Devices Having Vertical Channel Transistors and Related Methods 有权具有垂直沟道晶体管的半导体存储器件及相关方法公开(公告)号：US20090121268A1
公开(公告)日：2009-05-14
申请号：US12198266
申请日：2008-08-26
申请人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
发明人： Deok-hyung Lee , Sun-ghil Lee , Si-young Choi , Byeong-chan Lee , Seung-hun Lee
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10894 , H01L27/0207 , H01L27/10876 , H01L27/10882 , H01L27/10885
摘要： A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.
摘要翻译： 半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。 柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。 栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。 此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。 接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。 还讨论了相关方法。
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公开(公告)号：US08273620B2
公开(公告)日：2012-09-25
申请号：US12793809
申请日：2010-06-04
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译： 本发明的实施例提供一种半导体集成电路器件及其制造方法。 半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由 隔离区。 半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层 所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。
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公开(公告)号：US07755133B2
公开(公告)日：2010-07-13
申请号：US11855529
申请日：2007-09-14
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译： 本发明的实施例提供一种半导体集成电路器件及其制造方法。 半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由 隔离区。 半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层 所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。
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