公开(公告)号：US07081391B2

公开(公告)日：2006-07-25

申请号：US10722193

申请日：2003-11-26

申请人： Byeong-chan Lee ,  Si-young Choi ,  Jong-ryeol Yoo ,  Yong-hoon Son ,  In-soo Jung ,  Deok-hyung Lee

发明人： Byeong-chan Lee ,  Si-young Choi ,  Jong-ryeol Yoo ,  Yong-hoon Son ,  In-soo Jung ,  Deok-hyung Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/10873 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/10888

摘要： An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.

摘要翻译： 集成电路器件包括形成在集成电路器件的有源区上的栅电极和与有源区相邻的场隔离层。 源极区域和漏极区域在栅电极的交替侧上的有源区域中。 至少一个掩埋绝缘层位于漏极区域或源极区域之下。

公开(公告)号：US20050179073A1

公开(公告)日：2005-08-18

申请号：US10722193

申请日：2003-11-26

申请人： Byeong-chan Lee ,  Si-young Choi ,  Jong-ryeol Yoo ,  Yong-hoon Son ,  In-soo Jung ,  Deok-hyung Lee

发明人： Byeong-chan Lee ,  Si-young Choi ,  Jong-ryeol Yoo ,  Yong-hoon Son ,  In-soo Jung ,  Deok-hyung Lee

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L29/76

CPC分类号： H01L27/10873 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/10888

摘要： An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.

摘要翻译： 集成电路器件包括形成在集成电路器件的有源区上的栅电极和与有源区相邻的场隔离层。 源极区域和漏极区域在栅电极的交替侧上的有源区域中。 至少一个掩埋绝缘层位于漏极区域或源极区域之下。

公开(公告)号：US20060226455A1

公开(公告)日：2006-10-12

申请号：US11450725

申请日：2006-06-09

申请人： Byeong-chan Lee ,  Si-young Choi ,  Jong-ryeol Yoo ,  Yong-hoon Son ,  In-soo Jung ,  Deok-hyung Lee

发明人： Byeong-chan Lee ,  Si-young Choi ,  Jong-ryeol Yoo ,  Yong-hoon Son ,  In-soo Jung ,  Deok-hyung Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/10873 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/10888

摘要： An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.

公开(公告)号：US08373165B2

公开(公告)日：2013-02-12

申请号：US13343967

申请日：2012-01-05

申请人： Yong-hoon Son ,  Si-young Choi ,  Jong-wook Lee

发明人： Yong-hoon Son ,  Si-young Choi ,  Jong-wook Lee

IPC分类号： H01L29/04

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

摘要翻译： 一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层， 的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个 将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成 与单晶活性图案接触的栅电极。

公开(公告)号：US20110237055A1

公开(公告)日：2011-09-29

申请号：US13053291

申请日：2011-03-22

申请人： Yong-hoon Son ,  Si-Young Choi ,  Myoung-Bum Lee ,  Ki-Hyun Hwang ,  Seung-Jae Baik ,  Jeong Hee Han

发明人： Yong-hoon Son ,  Si-Young Choi ,  Myoung-Bum Lee ,  Ki-Hyun Hwang ,  Seung-Jae Baik ,  Jeong Hee Han

IPC分类号： H01L21/20

CPC分类号： H01L27/11578 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1207

摘要： A stacked semiconductor device that is reliable by forming an insulating layer on a lower memory layer and by forming a single crystalline semiconductor in portions of the insulating layer. A method of manufacturing the stacked semiconductor device, including: providing a lower memory layer including a plurality of lower memory structures; forming an insulating layer on the lower memory layer; forming trenches by removing portions of the insulating layer; forming a preparatory semiconductor layer for filling the trenches; and forming a single crystalline semiconductor layer by phase-changing the preparatory semiconductor layer.

摘要翻译： 通过在下部存储层上形成绝缘层，在绝缘层的一部分形成单晶半导体，可靠的叠层型半导体装置。 一种制造叠层半导体器件的方法，包括：提供包括多个下部存储结构的下部存储层; 在下部存储层上形成绝缘层; 通过去除绝缘层的部分形成沟槽; 形成用于填充沟槽的准备半导体层; 以及通过相变所述预备半导体层来形成单晶半导体层。

公开(公告)号：US07888246B2

公开(公告)日：2011-02-15

申请号：US12073315

申请日：2008-03-04

申请人： Yong-hoon Son ,  Si-young Choi ,  Jong-wook Lee

发明人： Yong-hoon Son ,  Si-young Choi ,  Jong-wook Lee

IPC分类号： H01L21/36

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

摘要翻译： 一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层， 的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个 将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成 与单晶活性图案接触的栅电极。

公开(公告)号：US08101509B2

公开(公告)日：2012-01-24

申请号：US13025011

申请日：2011-02-10

申请人： Yong-hoon Son ,  Si-young Choi ,  Jong-wook Lee

发明人： Yong-hoon Son ,  Si-young Choi ,  Jong-wook Lee

IPC分类号： H01L21/20

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

摘要翻译： 一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层， 的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个 将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成 与单晶活性图案接触的栅电极。

公开(公告)号：US20080217616A1

公开(公告)日：2008-09-11

申请号：US12073315

申请日：2008-03-04

申请人： Yong-hoon Son ,  Si-young Choi ,  Jong-wook Lee

发明人： Yong-hoon Son ,  Si-young Choi ,  Jong-wook Lee

IPC分类号： H01L29/04 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

摘要翻译： 一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层， 的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个 将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成 与单晶活性图案接触的栅电极。

公开(公告)号：US20170345843A1

公开(公告)日：2017-11-30

申请号：US15398081

申请日：2017-01-04

申请人： Eun-young Lee ,  Yong-hoon Son ,  Jae-young Ahn

发明人： Eun-young Lee ,  Yong-hoon Son ,  Jae-young Ahn

IPC分类号： H01L27/11582 ,  H01L29/10 ,  H01L23/528 ,  H01L23/522 ,  H01L23/544 ,  H01L27/1157 ,  H01L27/11573

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/1037 ,  H01L2223/544 ,  H01L2223/54426

摘要： A vertical memory device includes a plurality of stacked structures, at least one inter-structure layer, and a channel structure. The plurality of stacked structures comprises a plurality of gate electrodes and a plurality of insulation film patterns that are alternately and repeatedly stacked on a substrate. At least one inter-structure layer is positioned between the two stacked structures adjacent to each other from among the plurality of stacked structures. A channel structure penetrates the plurality of stacked structures and the at least one inter-structure layer, the channel structure extending in the first direction, the channel structure being connected to the substrate.

公开(公告)号：US08236673B2

公开(公告)日：2012-08-07

申请号：US13024924

申请日：2011-02-10

申请人： Yong-hoon Son ,  Jin-ha Jeong ,  Jung-ho Kim ,  Vladimir Urazaev ,  Jong-hyuk Kang ,  Sung-woo Hyun

发明人： Yong-hoon Son ,  Jin-ha Jeong ,  Jung-ho Kim ,  Vladimir Urazaev ,  Jong-hyuk Kang ,  Sung-woo Hyun

IPC分类号： H01L21/20

CPC分类号： H01L21/20

摘要： A method of fabricating a vertical NAND semiconductor device can include changing a phase of a first preliminary semiconductor layer in an opening from solid to liquid to form a first single crystalline semiconductor layer in the opening and then forming a second preliminary semiconductor layer on the first single crystalline semiconductor layer. The phase of the second preliminary semiconductor layer is changed from solid to liquid to form a second single crystalline semiconductor layer that combines with the first single crystalline semiconductor layers to form a single crystalline semiconductor layer in the opening.

摘要翻译： 制造垂直NAND半导体器件的方法可以包括将开口中的第一初级半导体层的相位从固体改变为在开口中形成第一单晶半导体层，然后在第一单个晶体管上形成第二初步半导体层 晶体半导体层。 第二初步半导体层的相位从固体变为液态，形成与第一单晶半导体层结合以在开口中形成单晶半导体层的第二单晶半导体层。