公开(公告)号：US07447795B2

公开(公告)日：2008-11-04

申请号：US10474500

申请日：2002-04-11

申请人： Kianoosh Naghshineh ,  Mark Stadler ,  Asgeir Thor Eiriksson

发明人： Kianoosh Naghshineh ,  Mark Stadler ,  Asgeir Thor Eiriksson

IPC分类号： G06F13/00

CPC分类号： G06F13/4027 ,  H04L49/102 ,  H04L49/103 ,  H04L49/201 ,  H04L49/30 ,  H04L49/351 ,  H04L49/354

摘要： A network interface controller includes a plurality of scatter gather circuits (104a-104d) connectable to a host via a bus (101). A packet buffer (112) is configured for communication with the scatter gather circuits (104a-104d). A plurality of access circuits (110a-110d) are configured to access external network connections. An optional forwarding engine (108) is selectable to generate routing information corresponding to data received via the access circuits (110a-110d) and to provide the routing information to the packet buffer (112).

摘要翻译： 网络接口控制器包括经由总线（101）可连接到主机的多个散射收集电路（104a-104d）。 分组缓冲器（112）被配置为与散射收集电路（104a-104d）通信。 多个访问电路（110a至110d）被配置为访问外部网络连接。 可选择的转发引擎（108）可选择以产生对应于经由访问电路（110a至110d）接收的数据的路由信息​​，并将路由信息提供给分组缓冲器（112）。

公开(公告)号：US06813652B2

公开(公告)日：2004-11-02

申请号：US10474499

申请日：2004-04-19

申请人： Mark Stadler ,  Asgeir Thor Eiriksson ,  Kianoosh Naghshineh

发明人： Mark Stadler ,  Asgeir Thor Eiriksson ,  Kianoosh Naghshineh

IPC分类号： G06F1300

CPC分类号： G06F13/28

摘要： A plurality of direct memory access data transfers are accomplished to transfer data from a host to an adaptor. For each transfer, an indication of locations of at least one group of storage locations associated with the host available to hold the data to be transferred to the host is provided from the host to the adaptor. An indication of the provided indication is maintained, for that transfer, by the host. Based on the indication of locations provided from the host to the adaptor, data is transferred to the at least one group of storage locations from the adaptor. An indication is provided from the adaptor to the host that the data transferring step has been completed with respect to the at least one group of storage locations. The host determines the locations corresponding to the at least one group of storage locations based on the indications maintained by the host and retrieving the data from the at least one group of storage locations based on the determination. A similar method is provided to transfer data from the adaptor to the host. Broadly speaking, the host and adaptor retain state information between DMA data transfers. As a result, absolute values of overhead items need not be transferred between the host CPU and the I/O device for each DMA data transfer, and the amount of overhead is reduced.

摘要翻译： 完成多个直接存储器访问数据传输以将数据从主机传送到适配器。 对于每个传送，从主机向适配器提供与可用于保存要传送到主机的数据相关联的主机的至少一组存储位置的位置的指示。 所提供的指示的指示由主机维护，用于该转移。 基于从主机向适配器提供的位置的指示，数据从适配器传送到至少一组存储位置。 从适配器向主机提供关于至少一组存储位置的数据传送步骤已经完成的指示。 主机基于由主机维护的指示，基于该确定从至少一组存储位置检索数据，来确定对应于至少一组存储位置的位置。 提供了类似的方法来将数据从适配器传输到主机。 一般来说，主机和适配器保留DMA数据传输之间的状态信息。 因此，对于每个DMA数据传输，开销项目的绝对值不需要在主机CPU和I / O设备之间传输，并且开销量减少。

公开(公告)号：US08032655B2

公开(公告)日：2011-10-04

申请号：US12255112

申请日：2008-10-21

申请人： Kianoosh Naghshineh ,  Mark D. Stadler ,  Asgeir Thor Eiriksson

发明人： Kianoosh Naghshineh ,  Mark D. Stadler ,  Asgeir Thor Eiriksson

IPC分类号： G06F13/00

CPC分类号： G06F13/4027 ,  H04L49/102 ,  H04L49/103 ,  H04L49/201 ,  H04L49/30 ,  H04L49/351 ,  H04L49/354

摘要： A network interface controller includes a plurality of scatter gather circuits (104a-104d) connectable to a host via a bus (101). A packet buffer (112) is configured for communication with the scatter gather circuits (104a-104d). A plurality of access circuits (110a-110d) are configured to access external network connections. An optional forwarding engine (108) is selectable to generate routing information corresponding to data received via the access circuits (110a-110d) and to provide the routing information to the packet buffer (112).

摘要翻译： 网络接口控制器包括经由总线（101）可连接到主机的多个散射收集电路（104a-104d）。 分组缓冲器（112）被配置为与散射收集电路（104a-104d）通信。 多个访问电路（110a-110d）被配置为访问外部网络连接。 可选择的转发引擎（108）可选择以产生对应于经由访问电路（110a-110d）接收的数据的路由信息​​，并将路由信息提供给分组缓冲器（112）。

公开(公告)号：US5121000A

公开(公告)日：1992-06-09

申请号：US666165

申请日：1991-03-07

申请人： Kianoosh Naghshineh

发明人： Kianoosh Naghshineh

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/00361

摘要： A CMOS output buffer circuit for providing an output signal at an output terminal which has a significant reduction in ground bounce over processing and power supply variations includes an output driver stage (12), a pull-up pre-driver circuit (14), a pull-down pre-diver circuit (16), and feedback means. The output driver stage is formed of a pull-up transistor (P1) and a pull-down transistor (N1). The feedback means is responsive to the output signal for controlling the rate of rise of the voltage at the gate electrode of the pull-down transistor so as to slow down its turn-on time when the output terminal is making a high-to-low transition, thereby significantly reducing the ground bounce. The feedback means is preferably formed of a capacitor (C2) having a first plate connected to the output terminal and a second plate coupled to the gate electrode of the pull-down transistor.

公开(公告)号：US4912341A

公开(公告)日：1990-03-27

申请号：US338584

申请日：1989-04-17

申请人： Kianoosh Naghshineh

发明人： Kianoosh Naghshineh

IPC分类号： H03K19/013

CPC分类号： H03K19/0136

摘要： A TTL buffer circuit includes an active turn-off means so as to provide faster output transitions without using excess power dissipation. The active turn-off means is formed of a Schottky diode (D402), a resistor (R417), and a Schottky bipolar transistor (Q414) which causes rapid switching of a pull-down transistor (Q413), thereby increasing the speed of the output transitions.

摘要翻译： TTL缓冲电路包括主动关断装置，以便提供更快的输出转换，而不用过多的功耗。 主动关断装置由肖特基二极管（D402），电阻器（R417）和肖特基双极晶体管（Q414）形成，其引起下拉晶体管（Q413）的快速切换，从而提高了 输出转换。

公开(公告)号：US5072136A

公开(公告)日：1991-12-10

申请号：US509916

申请日：1990-04-16

申请人： Kianoosh Naghshineh

发明人： Kianoosh Naghshineh

IPC分类号： H03K19/0175 ,  H03K19/003 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K19/00376

摘要： An ECL output buffer circuit for generating a stable predetermined output voltage over power supply, temperature and process variations and having a high speed of operation with low power consumption includes a differential pair formed of first and second input transistors (Q102, Q103), an emitter follower transistor (Q101), a first current source (112), and a second current source (114). The first current source is coupled to the base of the emitter follower transistor for generating a compensating current. The second current source is coupled to the emitters of the first and second input transistors for generating a gate current.

公开(公告)号：US4931673A

公开(公告)日：1990-06-05

申请号：US415754

申请日：1989-10-02

申请人： Kianoosh Naghshineh

发明人： Kianoosh Naghshineh

IPC分类号： H03K19/003 ,  H03K19/013 ,  H03K19/018

CPC分类号： H03K19/01812 ,  H03K19/00353 ,  H03K19/013 ,  H03K19/0136

摘要： An ECL-to-TTL translator circuit for converting ECL logic level signals to TTL logic level signals includes an active pull-down circuit (120), a high level voltage clamping circuit (122), and ground bounce protection circuit (124) so as to provide a higher speed of operation with minimal power dissipation and a significant reduction in ground bounce noise. The ground bounce protection circuit is formed of a voltage-independent current source, a reference resistor (R15), and a switching transistor (Q15).

摘要翻译： 用于将ECL逻辑电平信号转换为TTL逻辑电平信号的ECL至TTL转换器电路包括有源下拉电路（120），高电平钳位电路（122）和接地反弹保护电路（124），以便 以最小的功耗提供更高的操作速度，并显着降低地面反弹噪音。 地面反弹保护电路由电压无关的电流源，参考电阻（R15）和开关晶体管（Q15）构成。

公开(公告)号：US5124579A

公开(公告)日：1992-06-23

申请号：US636530

申请日：1990-12-31

申请人： Kianoosh Naghshineh

发明人： Kianoosh Naghshineh

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H03K19/003

CPC分类号： H03K19/00361

摘要： A CMOS output buffer circuit for providing an output signal at an output terminal with a significant reduction in ground bounce includes a pull-up driver circuit (12), a pull-down driver circuit (14), and a control circuit (16). The pull-up driver circuit includes first and second resistive means for delaying the turn-on times of pull-up transistors. The pull-down driver circuit includes third and fourth resistive elements for delaying the turn-on times of pull-down transistors. Each of the first through fourth resistive elements (D1-D4) is formed of a transmission gate and serves to control the gate-to-source voltages applied to the respective gates of the pull-up and pull-down transistors.

公开(公告)号：US4994691A

公开(公告)日：1991-02-19

申请号：US509649

申请日：1990-04-16

申请人： Kianoosh Naghshineh

发明人： Kianoosh Naghshineh

IPC分类号： H03K19/018

CPC分类号： H03K19/01812

摘要： A TTL-to-CML translator circuit includes a TTL input stage (20), a translation chain (22), a first CML differential pair (24), a level shifter (26), and a second CML differential pair (28). The first CML differential pair (24) is coupled between a TTL ground potential (GTTL) and a negative supply potential (VEE). The second CML differential pair (28) is connected between a CML ground potential (GCML) and the negative supply potential. The level shifter (26) serves to electrically isolate the TTL ground potential and the CML ground potential, thereby producing relatively noise free CML-compatible output signals.

公开(公告)号：US6154794A

公开(公告)日：2000-11-28

申请号：US716951

申请日：1996-09-08

申请人： Karim M. Abdalla ,  Kianoosh Naghshineh ,  James E. Tornes ,  Daniel Yau

发明人： Karim M. Abdalla ,  Kianoosh Naghshineh ,  James E. Tornes ,  Daniel Yau

IPC分类号： G06F3/14 ,  G06F13/14 ,  G06F13/20

CPC分类号： G06F3/14

摘要： A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device, very close to the processor, which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit. By placing these mechanisms close to the processor, rather than within the input/output unit, the system allows a larger portion of the input/output unit's buffer to be utilized for storing input/output data before a processor suspend or interrupt is required. This leads to increased input/output data throughput between the processor and the input/output unit by reducing processor interrupts. The system also includes an efficiently invoked timer mechanism for temporarily suspending the processor from transmitting stores to the input/output unit when the input/output unit and/or the intermediate devices are congested. The processor is not interrupted by an interrupt request until after the timer mechanism times out, allowing the system an opportunity to clear its congestion before a lengthily invoked interrupt is required.

摘要翻译： 一种用于控制计算机控制的图形系统内的输入/输出单元的信息流（例如，图形基元，显示数据等）的方法和装置。 该系统包括具有先进先出（FIFO）缓冲器，具有其FIFO缓冲器的单独输入/输出单元和耦合在输入/输出单元与多个FIFO缓冲器之间的多个中间设备（具有FIFO缓冲器） 处理器，用于将输入/输出数据从处理器移动到输入/输出单元。 机构位于非常接近处理器的中间设备内，其维持对输入/输出单元发送的输入/输出数据的数量的记账，但尚未从输入/输出单元的缓冲器中清除。 这些机制调节到输入/输出单元的数据流。 通过将这些机制放置在处理器附近，而不是在输入/输出单元内，系统允许输入/输出单元的缓冲区的较大部分用于在处理器挂起或中断之前存储输入/输出数据。 这导致通过减少处理器中断来增加处理器和输入/输出单元之间的输入/输出数据吞吐量。 当输入/输出单元和/或中间设备拥塞时，系统还包括有效地调用定时器机制，用于暂时将处理器从发送存储发送到输入/输出单元。 在定时器机制超时之后，处理器不会被中断请求中断，从而允许系统在需要长时间调用中断之前清除其拥塞。