公开(公告)号：US20220093187A1

公开(公告)日：2022-03-24

申请号：US17464898

申请日：2021-09-02

Applicant: Kioxia Corporation

Inventor： Rintaro IMAMURA ,  Hayato MASUBUCHI

IPC: G11C16/30 ,  G11C16/34

Abstract: A memory system according to at least one embodiment includes a semiconductor storage device and a controller. The semiconductor storage device includes an output transistor and a circuit for changing a magnitude of a current of the output transistor. The controller receives a signal output from the semiconductor storage device via the output transistor, and controls the circuit based on a level of the received signal.

公开(公告)号：US20230307433A1

公开(公告)日：2023-09-28

申请号：US18203693

申请日：2023-05-31

Applicant: Kioxia Corporation

Inventor： Hayato MASUBUCHI ,  Naoki KIMURA ,  Manabu MATSUMOTO ,  Toyota MORIMOTO

IPC: H01L25/18 ,  H05K1/02 ,  H05K3/30 ,  H10B69/00 ,  H01L23/498 ,  G11C5/02 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18 ,  H01L23/528 ,  H01L25/00

CPC classification number: H01L25/18 ,  H05K1/0225 ,  H05K1/0271 ,  H05K1/0298 ,  H05K3/305 ,  H10B69/00 ,  H01L23/49822 ,  G11C5/02 ,  H01L23/3142 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0655 ,  H05K1/181 ,  H01L23/5286 ,  H01L25/50 ,  H01L23/3121 ,  H05K2201/09136 ,  H05K2201/09681 ,  H05K2201/10159 ,  H01L2924/0002 ,  Y02P70/50

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

公开(公告)号：US20240405010A1

公开(公告)日：2024-12-05

申请号：US18805872

申请日：2024-08-15

Applicant: Kioxia Corporation

Inventor： Hayato MASUBUCHI ,  Naoki KIMURA ,  Manabu MATSUMOTO ,  Toyota MORIMOTO

IPC: H01L25/18 ,  G11C5/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/528 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30 ,  H10B69/00

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.