公开(公告)号：US11737281B2

公开(公告)日：2023-08-22

申请号：US17645133

申请日：2021-12-20

Applicant: Kioxia Corporation

Inventor： Harumi Seki ,  Kensuke Ota ,  Masumi Saitoh

IPC: H10B51/30 ,  H01L29/51 ,  H10B51/20 ,  H10B43/30 ,  H10B43/20 ,  H01L29/792

CPC classification number: H10B51/30 ,  H01L29/516 ,  H01L29/792 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20

Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a first insulating layer between the semiconductor layer and the first gate electrode layer; a second insulating layer between the first insulating layer and the first gate electrode layer, the second insulating layer having a first portion containing a ferroelectric material; and a first layer between the first insulating layer and the second insulating layer, the first layer containing silicon, nitrogen, and fluorine, the first layer having a first region and a second region between the first region and the second insulating layer, the first layer having a second atomic ratio of nitrogen to silicon in the second region higher than a first atomic ratio of nitrogen to silicon in the first region, and the first layer having fluorine concentration higher than the second region.

公开(公告)号：US11514970B2

公开(公告)日：2022-11-29

申请号：US17470802

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Marina Yamaguchi ,  Kensuke Ota ,  Kazuhiko Yamamoto ,  Masumi Saitoh

IPC: G11C11/22

Abstract: A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted.

公开(公告)号：US12033718B2

公开(公告)日：2024-07-09

申请号：US17944725

申请日：2022-09-14

Applicant: Kioxia Corporation

Inventor： Kensuke Ota ,  Marina Yamaguchi ,  Masatoshi Yoshikawa

IPC: G11C7/10 ,  G06N20/00 ,  G11C7/14

CPC classification number: G11C7/1096 ,  G06N20/00 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/14

Abstract: A semiconductor device according to an embodiment includes first to fifth interconnects, first to third memory cells, and a control circuit. The control circuit is configured to execute machine learning. Each of the first memory cells, the second memory cells, and the third memory cells includes a resistance changing element. In the machine learning, the control circuit is configured to: execute a write operation using a common write voltage to each of the second memory cells; and after the write operation, input input data to each of the first interconnects, and change a resistance value of at least one third memory cell of the third memory cells based on the input data and a signal output from each of the fifth interconnects based on the input data.

公开(公告)号：US11605647B2

公开(公告)日：2023-03-14

申请号：US17189197

申请日：2021-03-01

Applicant: KIOXIA CORPORATION

Inventor： Yusuke Tanaka ,  Masumi Saitoh ,  Kensuke Ota

IPC: H01L27/11597 ,  H01L29/51 ,  H01L29/24 ,  H01L27/1159 ,  H01L29/66 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor memory device includes a ferroelectric layer and a first semiconductor layer. The first semiconductor layer is electrically connected to a first electrode and a second electrode and includes an n-type oxide semiconductor. A third electrode is opposite the first semiconductor layer. The ferroelectric layer is between the third electrode and the first semiconductor layer. A second semiconductor layer includes at least one of a Group IV semiconductor material or a p-type oxide semiconductor material. The first semiconductor layer is between the ferroelectric layer and the second semiconductor layer.

公开(公告)号：US11574958B2

公开(公告)日：2023-02-07

申请号：US17470839

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Daisuke Matsubayashi ,  Kensuke Ota

IPC: H01L27/28 ,  H01L51/05 ,  H01L27/11582 ,  G11C16/06

Abstract: A memory device according to an embodiment includes a fluid layer extending in a first direction, a particle in the fluid layer, a first control electrode made of a first material, a first insulating film provided between the fluid layer and the first control electrode, a second control electrode made of a second material and provided to be spaced apart from the first control electrode in the first direction, a second insulating film provided between the fluid layer and the second control electrode, a third control electrode made of a third material different from the first material and the second material and provided between the first control electrode and the second control electrode, and a third insulating film provided between the fluid layer and the third control electrode.

公开(公告)号：US11195844B2

公开(公告)日：2021-12-07

申请号：US16804403

申请日：2020-02-28

Applicant: Kioxia Corporation

Inventor： Kensuke Ota ,  Masumi Saitoh ,  Kiwamu Sakuma

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11539 ,  H01L27/11519

Abstract: A semiconductor memory device includes a substrate, a plurality of conductive layers, a first semiconductor layer, a memory portion, and a drive circuit which drives the memory cell. The conductive layers are provided in a first region, a second region, and a third region different from the first region and the second region, and a portion positioned in the third region is insulated from a portion positioned in the first region and the second region. The drive circuit is provided in the third region, and includes a second semiconductor layer, and an insulating layer, and one end of the second semiconductor layer is connected to the conductive layers in the second region and the other end of the second semiconductor layer is connected to the substrate.