公开(公告)号：US11482269B2

公开(公告)日：2022-10-25

申请号：US17199726

申请日：2021-03-12

Applicant: Kioxia Corporation

Inventor： Kunifumi Suzuki ,  Kiwamu Sakuma

IPC: G11C11/22 ,  H01L27/11514 ,  H01L27/11597

Abstract: A semiconductor memory device includes a first memory transistor, a first memory capacitor, and a control circuit connected to them. The first memory transistor includes a first gate electrode, a first semiconductor layer, and a first insulating film containing an insulating material. The first memory capacitor includes a first electrode, a second electrode, and a second insulating film containing the insulating material of the first insulating film. The control circuit is configured to perform a first program operation that supplies the first gate electrode with a first program voltage, a second program operation that supplies the first gate electrode with a second program voltage larger than the first program voltage, and a first read operation that supplies at least one of the first electrode or the second electrode with a voltage. The control circuit performs the first or the second program operation after performing the first read operation.

公开(公告)号：US11430500B2

公开(公告)日：2022-08-30

申请号：US17189097

申请日：2021-03-01

Applicant: KIOXIA CORPORATION

Inventor： Haruka Sakuma ,  Kiwamu Sakuma ,  Masumi Saitoh

IPC: G11C11/22 ,  H01L29/51 ,  H01L27/11592 ,  H01L27/11587 ,  H01L27/1159

Abstract: A semiconductor storage device includes a plurality of gate electrodes, a semiconductor layer facing the plurality of gate electrodes, a gate insulating layer arranged between each of the plurality of gate electrodes and the semiconductor layer. The gate insulating layer contains oxygen (O) and hafnium (Hf) and has an orthorhombic crystal structure. A plurality of first wirings is connected to the respective gate electrodes. A controller is configured to execute a write sequence and an erasing sequence by applying certain voltages to at least one of the first wirings. The controller is further configured to increase either a program voltage to be applied to the first wirings in the write sequence or an application time of the program voltage in the write sequence after a total number of executions of the write sequence or the erasing sequence has reached a particular number.

公开(公告)号：US20250017020A1

公开(公告)日：2025-01-09

申请号：US18762786

申请日：2024-07-03

Applicant: Kioxia Corporation

Inventor： Yoko YOSHIMURA ,  Kiwamu Sakuma ,  Kunifumi SUZUKI ,  Hidesato ISHIDA

IPC: H10B51/20 ,  H01L21/28 ,  H01L23/528 ,  H01L23/532 ,  H01L29/51

Abstract: A semiconductor memory device includes a semiconductor layer; a gate electrode; a first insulating film provided between the semiconductor layer and the gate electrode, and including at least one of oxygen, hafnium, or a first additive element; and a second insulating film provided between the first insulating film and the gate electrode. The first insulating film includes a first additive region, a second additive region provided between the first additive region and the gate electrode, and a memory region provided between the first additive region and the second additive region. The first additive region includes a second additive element selected from a group consisting of ruthenium, titanium, molybdenum, tantalum, tungsten, platinum, and combinations thereof. The second additive region includes a third additive element selected group consisting of ruthenium, titanium, molybdenum, tantalum, tungsten, platinum, and combinations thereof.

公开(公告)号：US11195844B2

公开(公告)日：2021-12-07

申请号：US16804403

申请日：2020-02-28

Applicant: Kioxia Corporation

Inventor： Kensuke Ota ,  Masumi Saitoh ,  Kiwamu Sakuma

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11539 ,  H01L27/11519

Abstract: A semiconductor memory device includes a substrate, a plurality of conductive layers, a first semiconductor layer, a memory portion, and a drive circuit which drives the memory cell. The conductive layers are provided in a first region, a second region, and a third region different from the first region and the second region, and a portion positioned in the third region is insulated from a portion positioned in the first region and the second region. The drive circuit is provided in the third region, and includes a second semiconductor layer, and an insulating layer, and one end of the second semiconductor layer is connected to the conductive layers in the second region and the other end of the second semiconductor layer is connected to the substrate.

公开(公告)号：US12261221B2

公开(公告)日：2025-03-25

申请号：US17686215

申请日：2022-03-03

Applicant: Kioxia Corporation

Inventor： Kiwamu Sakuma ,  Taro Shiokawa ,  Keiko Sakuma

IPC: H01L29/786 ,  H01L29/66 ,  H10B12/00 ,  H10B41/35 ,  H10B43/35

Abstract: A transistor includes an upper electrode; a lower electrode; a gate electrode disposed between the upper electrode and the lower electrode; and a columnar portion penetrating the gate electrode and provided between the upper electrode and the lower electrode. The columnar portion includes a tubular gate insulating film and a semiconductor layer, the tubular gate insulating film disposed at a first distance away from the upper electrode and in contact with the gate electrode. The semiconductor layer is embedded in the tubular gate insulating film and between the gate insulating film and the upper electrode and in contact with the upper electrode.

公开(公告)号：US11871557B2

公开(公告)日：2024-01-09

申请号：US17690425

申请日：2022-03-09

Applicant: Kioxia Corporation

Inventor： Taro Shiokawa ,  Kiwamu Sakuma ,  Keiko Sakuma

IPC: H01L27/108 ,  H10B12/00 ,  H01L29/786

CPC classification number: H10B12/30 ,  H01L29/7869 ,  H01L29/78642

Abstract: A semiconductor device according to the embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode opposed to the oxide semiconductor layer; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; a first insulating layer provided between the gate electrode and the first electrode; and a second insulating layer provided between the gate electrode and the second electrode and having an oxygen atom concentration lower than an oxygen atom concentration of the first insulating layer.

公开(公告)号：US11665908B2

公开(公告)日：2023-05-30

申请号：US17028748

申请日：2020-09-22

Applicant: Kioxia Corporation

Inventor： Haruka Sakuma ,  Hidenori Miyagawa ,  Shosuke Fujii ,  Kiwamu Sakuma ,  Fumitaka Arai ,  Kunifumi Suzuki

IPC: H01L21/28 ,  H01L27/11597 ,  H01L29/51 ,  H01L27/1159

CPC classification number: H01L27/11597 ,  H01L27/1159 ,  H01L29/40111 ,  H01L29/516

Abstract: A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.

公开(公告)号：US20230088455A1

公开(公告)日：2023-03-23

申请号：US17690425

申请日：2022-03-09

Applicant: Kioxia Corporation

Inventor： Taro Shiokawa ,  Kiwamu Sakuma ,  Keiko Sakuma

IPC: H01L27/108 ,  H01L29/786

Abstract: A semiconductor device according to the embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode opposed to the oxide semiconductor layer; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; a first insulating layer provided between the gate electrode and the first electrode; and a second insulating layer provided between the gate electrode and the second electrode and having an oxygen atom concentration lower than an oxygen atom concentration of the first insulating layer.