公开(公告)号：US11977481B2

公开(公告)日：2024-05-07

申请号：US18310597

申请日：2023-05-02

Applicant: KIOXIA CORPORATION

Inventor： Kazuhiro Fukutomi ,  Kenichiro Yoshii ,  Shinichi Kanno ,  Shigehiro Asano

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/00 ,  G06F12/16 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/16 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0638 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/0688 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/7202 ,  G06F2212/7205

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

公开(公告)号：US12259813B2

公开(公告)日：2025-03-25

申请号：US18624930

申请日：2024-04-02

Applicant: KIOXIA CORPORATION

Inventor： Kazuhiro Fukutomi ,  Kenichiro Yoshii ,  Shinichi Kanno ,  Shigehiro Asano

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/00 ,  G06F12/16 ,  G06F13/16

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

公开(公告)号：US11947422B2

公开(公告)日：2024-04-02

申请号：US18316531

申请日：2023-05-12

Applicant: KIOXIA CORPORATION

Inventor： Kenichiro Yoshii ,  Shinichi Kanno

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/1009

CPC classification number: G06F11/1068 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/1009 ,  G06F2212/1044

Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

公开(公告)号：US11747979B2

公开(公告)日：2023-09-05

申请号：US17235144

申请日：2021-04-20

Applicant: Kioxia Corporation

Inventor： Tetsuya Sunata ,  Daisuke Iwai ,  Kenichiro Yoshii

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/2022

Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.

公开(公告)号：US11693734B2

公开(公告)日：2023-07-04

申请号：US17449994

申请日：2021-10-05

Applicant: Kioxia Corporation

Inventor： Kenichiro Yoshii ,  Shinichi Kanno

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/1009

CPC classification number: G06F11/1068 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/1009 ,  G06F2212/1044

Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

公开(公告)号：US11411016B2

公开(公告)日：2022-08-09

申请号：US17005535

申请日：2020-08-28

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Keisuke Nakatsuka ,  Hiroshi Maejima ,  Kenichiro Yoshii ,  Takashi Maeda ,  Hideo Wada

IPC: H01L27/11565 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11578 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11563 ,  H01L27/11568

Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.

公开(公告)号：US11675697B2

公开(公告)日：2023-06-13

申请号：US17590310

申请日：2022-02-01

Applicant: KIOXIA CORPORATION

Inventor： Kazuhiro Fukutomi ,  Kenichiro Yoshii ,  Shinichi Kanno ,  Shigehiro Asano

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/00 ,  G06F12/16 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/16 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0638 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/0688 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/7202 ,  G06F2212/7205

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

公开(公告)号：US11871576B2

公开(公告)日：2024-01-09

申请号：US17113285

申请日：2020-12-07

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Mie Matsuo ,  Kenichiro Yoshii ,  Koichiro Shindo ,  Kazushige Kawasaki ,  Tomoya Sanuki

IPC: H10B43/40 ,  H01L25/065 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50 ,  H01L21/18 ,  H01L21/768 ,  H01L23/00

CPC classification number: H10B43/40 ,  H01L21/185 ,  H01L21/76898 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50 ,  H01L2224/08145

Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

公开(公告)号：US11520496B2

公开(公告)日：2022-12-06

申请号：US17108311

申请日：2020-12-01

Applicant: Kioxia Corporation

Inventor： Daisuke Iwai ,  Kenichiro Yoshii ,  Tetsuya Sunata

IPC: G06F3/06

Abstract: According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.

公开(公告)号：US11307797B2

公开(公告)日：2022-04-19

申请号：US16290633

申请日：2019-03-01

Applicant: Kioxia Corporation

Inventor： Tetsuya Sunata ,  Daisuke Iwai ,  Kenichiro Yoshii

IPC: G06F3/06 ,  G06F12/02

Abstract: According to one embodiment, a storage device is accessible by an external device via an interface and includes a nonvolatile memory including one or more blocks, and a controller electrically connected to the nonvolatile memory. The controller receives from the external device a request and a notification indicating that a response performance of the request is to be lowered. In response to receiving the request and notification, the controller determines a response time longer than a processing time of the request, and executes a first performance lowering process that executes a block managing process of the nonvolatile memory by using an idle time which is a difference between the response time and the processing time of the request or executes a second performance lowering process that lowers the response performance so as to process the request by spending the response time.