公开(公告)号：US20240196615A1

公开(公告)日：2024-06-13

申请号：US18461827

申请日：2023-09-06

Applicant: Kioxia Corporation

Inventor： Takuya NISHIKAWA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A semiconductor memory device includes finger structures arranged in a first direction and an inter-finger insulating member disposed between a first finger structure and a second finger structure. The first finger structure includes conductive layers stacked in a stacking direction, a semiconductor column opposed to the conductive layers, a first insulating layer and a second insulating layer covering terrace portions of the conductive layers, and a third insulating layer disposed between the first insulating layer and the inter-finger insulating member in the first direction. The second insulating layer and the third insulating layer have mutually same main components. At least a part of a main component of the first insulating layer is different from the main components of the second insulating layer and the third insulating layer. The second insulating layer and the third insulating layer have mutually different etching rates.

公开(公告)号：US20210288058A1

公开(公告)日：2021-09-16

申请号：US17152902

申请日：2021-01-20

Applicant: Kioxia Corporation

Inventor： Takahito NISHIMURA ,  Takuya NISHIKAWA ,  Shihoko ASAI

IPC: H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory device according to an embodiment includes a substrate, first members, first conductive layers, and first and second pillars. The substrate includes first and second areas, and block areas. The first conductive layers are split by the first members. The first pillars are provided in an area in which the first area and the block areas overlap. The second pillars are provided in an area in which the second area and the block areas overlap. The second area includes a first sub-area in which the second pillars are periodically arranged in an area that overlaps at least one block area in the block areas. In the first sub-area, at least one second pillar is omitted from the second pillars that are periodically arranged.

公开(公告)号：US20240064980A1

公开(公告)日：2024-02-22

申请号：US18159634

申请日：2023-01-25

Applicant: Kioxia Corporation

Inventor： Takuya NISHIKAWA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A semiconductor memory device includes stacked conductive layers, a first insulating layer above the conductive layers in a stacking direction, and a second insulating layer above the first insulating layer and the conductive layers. A first semiconductor pillar extends in the stacking direction through the conductive layers and the first insulating layer. A first charge storage film is between the conductive layers and the first semiconductor pillar. A via contact electrode extends in the stacking direction through the second insulating layer and is connected to a first end of the first semiconductor pillar. The first insulating layer comprises a material different from that of the second insulating layer.

公开(公告)号：US20210249434A1

公开(公告)日：2021-08-12

申请号：US16944552

申请日：2020-07-31

Applicant: Kioxia Corporation

Inventor： Takuya NISHIKAWA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor storage device in an embodiment includes a stacked body including a plurality of conductive layers stacked with an insulating layer interposed therebetween, end portions of the plurality of conductive layers being arranged like stairs in a stair portion, a plurality of memory cells each disposed in a crossing portion of at least a part of the plurality of conductive layers and a pillar extending in a stacking direction of the plurality of conductive layers in the stacked body, a first structure having a longitudinal direction in a first direction crossing the stacking direction and dividing the stacked body, and a second structure disposed in the stair portion, extending in a second direction toward the first structure, extending in the stacking direction in the stacked body, and having a width wider at a first portion farther from the first structure than at a second portion closer to the first structure.

公开(公告)号：US20240260271A1

公开(公告)日：2024-08-01

申请号：US18525945

申请日：2023-12-01

Applicant: Kioxia Corporation

Inventor： Takuya NISHIKAWA

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/528 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor memory device according to an embodiment includes a first conductor, first to third insulators, a second conductor, and a memory pillar. The first conductor and the first insulator are arranged in a first direction. The second conductor extends in the first direction to penetrate the first conductor and the first insulator. The memory pillar extends in the first direction to penetrate the first conductor and the first insulator, and includes a semiconductor. The second insulator is provided between the first conductor and the second conductor. The third insulator includes a first portion between the second insulator and the first conductor, a portion on a surface on one side of the second insulator in the first direction, and a portion on a surface on the other side of the second insulator in the first direction. The third insulator offers an etching rate smaller than the second insulator.

公开(公告)号：US20240121962A1

公开(公告)日：2024-04-11

申请号：US18461326

申请日：2023-09-05

Applicant: Kioxia Corporation

Inventor： Satoshi NAGASHIMA ,  Shota KASHIYAMA ,  Tadashi IGUCHI ,  Takuya NISHIKAWA

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: According to one embodiment, a semiconductor device includes a stacked film with first insulating films and electrode layers alternately stacked in a first direction. The device further includes a columnar portion extending in the first direction and provided in a first region of the stacked film. The columnar portion forms memory cells at its intersections with the electrode layers. The device further includes a support column portion provided in a second region and extending in the first direction. A conductive plug is provided on a first electrode layer among the electrode layers in the second region. A first side surface of the support column portion faces a second side surface of the plug and the second side surface is concave in a direction toward the first side surface.

公开(公告)号：US20230200071A1

公开(公告)日：2023-06-22

申请号：US17840686

申请日：2022-06-15

Applicant: Kioxia Corporation

Inventor： Takahito NISHIMURA ,  Takuya NISHIKAWA

IPC: H01L27/11582 ,  H01L27/11531

CPC classification number: H01L27/11582 ,  H01L27/11531

Abstract: According to one embodiment, a semiconductor memory device includes: a first stacked body that includes a memory region, a stepped region, and a connection region arranged in a first direction; a plurality of first pillars that is disposed in the memory region, extends in the first stacked body in the stacking direction; a plurality of second pillars that includes a second insulating layer, has a layer structure different from a layer structure of the first pillars, and extends in the stacking direction in a position overlapping a stepped portion disposed in the stepped region in the stacking direction; and a plurality of third pillars that extends in the first stacked body in the stacking direction, and has a same layer structure as the layer structure of the first pillars, at least a part of the plurality of third pillars being disposed in the connection region.

公开(公告)号：US20230301107A1

公开(公告)日：2023-09-21

申请号：US17883464

申请日：2022-08-08

Applicant: KIOXIA CORPORATION

Inventor： Takuya NISHIKAWA

IPC: H01L27/1157 ,  H01L27/11578

CPC classification number: H01L27/1157 ,  H01L27/11578

Abstract: According to one embodiment, a semiconductor storage device includes a stacked body with conductive layers which are spaced apart one from another along a first direction. A pillar structure extends in the first direction through the conductive layers and has protruding parts, each of which protrudes outwardly from the pillar structure towards a conductive layer. The pillar structure includes a semiconductor layer, a tunnel insulating layers separately in each of the protruding parts between the semiconductor layer and the conductive layer. There is no tunnel insulating layer in the region between the adjacent protruding parts in the first direction. A charge storage layer is also separately in each protruding part between the tunnel insulating layer and the conductive layer.

公开(公告)号：US20220085062A1

公开(公告)日：2022-03-17

申请号：US17199878

申请日：2021-03-12

Applicant: Kioxia Corporation

Inventor： Wataru UNNO ,  Takuya NISHIKAWA ,  Jun TAKEKIDA ,  Kazuhiro NAKANISHI

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556

Abstract: According to one embodiment, a semiconductor memory device includes a pair of first plate-shaped portions that extends in a stacking direction of respective layers of a first stacked body and a first direction crossing the stacking direction, and is in contact with a second stacked body on both sides of the second stacked body in a second direction crossing the stacking direction and the first direction, a pair of second plate-shaped portions of which longitudinal direction is in the first direction, the pair of second plate-shaped portions extending through the first stacked body in the stacking direction on both sides of the pair of first plate-shaped portions in the second direction in positions apart from the pair of first plate-shaped portions, and a columnar portion that extends through the first stacked body in the stacking direction in a position between one of the first plate-shaped portions out of the pair of first plate-shaped portions and one of the second plate-shaped portions, that faces the one of the first plate-shaped portions, out of the pair of second plate-shaped portions, and includes a first material having a high ultraviolet-light blocking capability.