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37 条记录 (耗时 0.025 秒)

    Low trigger voltage, low leakage ESD NFET
    1.
    发明授权
    Low trigger voltage, low leakage ESD NFET 失效
    低触发电压，低漏电ESD NFET

    公开(公告)号：US07098513B2

    公开(公告)日：2006-08-29

    申请号：US10905682

    申请日：2005-01-17

    申请人： Kiran V. Chatty ,  Robert J. Gauthier ,  Terence B. Hook ,  Christopher S. Putnam ,  Mujahid Muhammad

    发明人： Kiran V. Chatty ,  Robert J. Gauthier ,  Terence B. Hook ,  Christopher S. Putnam ,  Mujahid Muhammad

    IPC分类号： H01L29/76

    CPC分类号： H01L29/78 ,  H01L27/027

    摘要： A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.

    摘要翻译： 具有相关联的寄生横向npn双极结型晶体管的场效应晶体管包括衬底中的源极区域，与源极区域横向相邻的衬底中的沟道区域，衬底中的与沟道区域横向相邻的漏极区域，以及位于 衬底的沟道区域。 此外，衬底的降低的触发电压区域位于漏极区域的下方。 降低的触发电压区域具有约零的阈值电压，并且包括纯晶片衬底的未掺杂区域。 因此，降低的触发电压区域没有注入的N型和P型掺杂。

    High voltage ESD power clamp
    2.
    发明授权
    High voltage ESD power clamp 有权
    高压ESD电源钳

    公开(公告)号：US07457086B2

    公开(公告)日：2008-11-25

    申请号：US11614659

    申请日：2006-12-21

    申请人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mahmoud A. Mousa ,  Mujahid Muhammad ,  Christopher S. Putnam

    发明人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mahmoud A. Mousa ,  Mujahid Muhammad ,  Christopher S. Putnam

    IPC分类号： H02H3/20 ,  H02H3/22 ,  H02H9/04

    CPC分类号： H01L27/0266 ,  H03K17/08142

    摘要： Method and device for protecting against electrostatic discharge. The method includes configuring a gate of at least one upper transistor of a transistor network connected between power rails to be biased to a prescribed value, and coupling an electrostatic discharge event to a gate of a lower transistor of the transistor network. The at least one upper and at least one lower transistors of the transistor network are respectively coupled between the power rails from a higher voltage to a lower voltage.

    摘要翻译： 用于防止静电放电的方法和装置。 该方法包括配置连接在电源轨之间的晶体管网络的至少一个上晶体管的栅极以被偏置到规定值，以及将静电放电事件耦合到晶体管网络的下晶体管的栅极。 晶体管网络的至少一个上部和至少一个下部晶体管分别从较高电压到较低电压耦合在电源轨之间。

    High voltage ESD power clamp
    3.
    发明授权
    High voltage ESD power clamp 失效
    高压ESD电源钳

    公开(公告)号：US07203045B2

    公开(公告)日：2007-04-10

    申请号：US10711748

    申请日：2004-10-01

    申请人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mahmoud A. Mousa ,  Mujahid Muhammad ,  Christopher S. Putnam

    发明人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mahmoud A. Mousa ,  Mujahid Muhammad ,  Christopher S. Putnam

    IPC分类号： H02H3/20 ,  H02H3/22 ,  H02H9/00 ,  H02H9/04

    CPC分类号： H01L27/0266 ,  H03K17/08142

    摘要： A structure and apparatus is provided for an electrostatic discharge power clamp, for use with high voltage power supplies. The power clamp includes a network of transistor devices, for example, nFETs arranged in series between a power rail and a ground rail. The first transistor device is biased into a partially on-state, and thus, neither device sees the full voltage potential between the power rail and the ground rail. Accordingly, the power clamp can function in voltage environments higher than the native voltage of the transistor devices. Additionally, the second transistor device is controlled by an RC network functioning as a trigger which allows the second transistor device to turn on during a voltage spike such as occurs during an ESD event. The capacitor of the RC network may be small thereby requiring small real estate on the integrated circuit. The clamp may have fast turn-on times as well as conducting current for long periods of time after turning on.

    摘要翻译： 为静电放电电源钳提供一种用于高压电源的结构和装置。 功率钳包括晶体管器件网络，例如串联布置在电源轨和接地轨之间的nFET。 第一晶体管器件被偏置成部分导通状态，因此，两个器件都不会看到电源轨和接地轨之间的全电压电位。 因此，功率钳可以在高于晶体管器件的天然电压的电压环境中工作。 此外，第二晶体管器件由用作触发器的RC网络控制，该RC网络允许第二晶体管器件在诸如在ESD事件期间发生的电压尖峰期间导通。 RC网络的电容器可能很小，从而在集成电路上需要小的空间。 打开后，夹具可能会导通快速导通时间，并长时间传导电流。

    Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing
    4.
    发明授权
    Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing 失效
    用于通过在处理期间去除多晶硅栅极来产生自对准SOI二极管的方法

    公开(公告)号：US07138313B2

    公开(公告)日：2006-11-21

    申请号：US10708912

    申请日：2004-03-31

    申请人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad ,  Christopher S. Putnam

    发明人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad ,  Christopher S. Putnam

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66136 ,  H01L29/861

    摘要： A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, the plurality of diffusion regions separated by a diode junction, wherein the implanting aligns an upper surface of the diode junction with the protective structure; and removing the protective structure. The method further comprises forming a silicide layer over the diffusion regions and aligned with the protective structure. The protective structure comprises a hard mask, wherein the hard mask comprises a silicon nitride layer. Alternatively, the protective structure comprises a polysilicon gate and insulating spacers on opposite sides of the gate. Furthermore, in the removing step, the spacers remain on the substrate.

    摘要翻译： 一种形成自对准SOI二极管的方法，所述方法包括在衬底上沉积保护结构; 在衬底中的至少一对隔离区域之间的区域中注入多个可变掺杂剂类型的扩散区域，所述多个扩散区域被二极管结点隔开，其中所述注入将所述二极管结的上表面与所述保护层 结构体; 并移除保护结构。 该方法还包括在扩散区上形成硅化物层并与保护结构对准。 保护结构包括硬掩模，其中硬掩模包括氮化硅层。 或者，保护结构包括在栅极的相对侧上的多晶硅栅极和绝缘间隔物。 此外，在去除步骤中，衬垫保留在衬底上。

    ESD field-effect transistor and integrated diffusion resistor
    6.
    发明授权
    ESD field-effect transistor and integrated diffusion resistor 有权
    ESD场效应晶体管和集成扩散电阻

    公开(公告)号：US08513738B2

    公开(公告)日：2013-08-20

    申请号：US13188094

    申请日：2011-07-21

    申请人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    发明人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    IPC分类号： H01L23/60

    CPC分类号： H01L29/41775 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.

    摘要翻译： 静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。 第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。 可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。 静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

    Electrical overstress protection circuit
    10.
    发明授权
    Electrical overstress protection circuit 有权
    电气过载保护电路

    公开(公告)号：US08363367B2

    公开(公告)日：2013-01-29

    申请号：US12632015

    申请日：2009-12-07

    申请人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

    发明人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0251 ,  G06F17/5045

    摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.

    摘要翻译： 提供了一种用于电力过应力（EOS）保护的半导体电路。 半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。 连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。 特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。 可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。