公开(公告)号：US20080014698A1

公开(公告)日：2008-01-17

申请号：US11457620

申请日：2006-07-14

申请人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

发明人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

摘要翻译： 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺，以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US20120132979A1

公开(公告)日：2012-05-31

申请号：US13365472

申请日：2012-02-03

申请人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

发明人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

摘要翻译： 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US20110013463A1

公开(公告)日：2011-01-20

申请号：US12892691

申请日：2010-09-28

申请人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

发明人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC分类号： G11C11/34

CPC分类号： H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

摘要翻译： 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US07485528B2

公开(公告)日：2009-02-03

申请号：US11457620

申请日：2006-07-14

申请人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

发明人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

摘要翻译： 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US07824994B2

公开(公告)日：2010-11-02

申请号：US12271132

申请日：2008-11-14

申请人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

发明人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

摘要翻译： 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US20090068812A1

公开(公告)日：2009-03-12

申请号：US12271132

申请日：2008-11-14

申请人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

发明人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

摘要翻译： 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺，以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US07279710B2

公开(公告)日：2007-10-09

申请号：US11231090

申请日：2005-09-20

申请人： Michael Smith ,  Mark Helm ,  Kirk Prall

发明人： Michael Smith ,  Mark Helm ,  Kirk Prall

IPC分类号： H01L29/10

CPC分类号： H01L29/66621 ,  H01L21/76224

摘要： An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation.

摘要翻译： 制造具有非导电侧壁的沟槽栅极的集成电路晶体管。 晶体管由填充有非导电材料的隔离沟道围绕。 栅极沟槽的侧壁由非导电材料形成，并且基本上没有未蚀刻的衬底材料。 结果，栅极沟槽的侧壁在晶体管的源极和漏极之间不形成不期望的导电路径，从而有利地减少在工作期间在源极和漏极之间流动的寄生电流的量。

公开(公告)号：US07115509B2

公开(公告)日：2006-10-03

申请号：US10714752

申请日：2003-11-17

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/44

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

摘要翻译： 描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。 使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。 通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。 低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

公开(公告)号：US07072217B2

公开(公告)日：2006-07-04

申请号：US10785785

申请日：2004-02-24

申请人： Kirk Prall

发明人： Kirk Prall

IPC分类号： G11C16/04

CPC分类号： H01L29/7887 ,  H01L29/7923

摘要： A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.

公开(公告)号：US20050285148A1

公开(公告)日：2005-12-29

申请号：US11217739

申请日：2005-09-01

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/48 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

摘要翻译： 描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。 使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。 通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。 低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。