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公开(公告)号：US20080282251A1
公开(公告)日：2008-11-13
申请号：US11746998
申请日：2007-05-10
CPC分类号： G06F9/485 , G06F9/3009 , G06F9/3013 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.
摘要翻译： 公开了一种用于在处理器处调度线程执行的技术。 该技术包括执行线程的线程去加重指令，该线程去加强线程，直到与线程相关联的等待存储器事务（例如高速缓存未命中）的数量处于或低于阈值。 当该线程被去加强时，处理器中具有较高优先级的其他线程可以执行或分配系统资源。 因此，处理器中失速的可能性降低。
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公开(公告)号：US08832702B2
公开(公告)日：2014-09-09
申请号：US11746998
申请日：2007-05-10
CPC分类号： G06F9/485 , G06F9/3009 , G06F9/3013 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.
摘要翻译： 公开了一种用于在处理器处调度线程执行的技术。 该技术包括执行线程的线程去加重指令，其不强调线程，直到与该线程相关联的等待存储器事务（例如高速缓存未命中）的数量处于或低于阈值。 当该线程被去加强时，处理器中具有较高优先级的其他线程可以执行或分配系统资源。 因此，处理器中失速的可能性降低。
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公开(公告)号：US20080209182A1
公开(公告)日：2008-08-28
申请号：US11679590
申请日：2007-02-27
IPC分类号： G06F9/302
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30189 , G06F9/342
摘要： A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.
摘要翻译： 公开了一种数据处理装置及其方法。 数据处理设备可以在三种不同的模式下工作。 在第一N位模式中，数据处理装置根据N位值执行存储器访问，并使用N位值执行算术运算。 在第二种混合N比特/ M比特模式中，数据处理装置基于M比特值执行存储器访问，其中M小于N，并且使用N比特值进行算术运算。 在第三个M位模式中，数据处理设备基于M位值执行存储器访问，并使用M位值执行算术运算。 这三种模式提供与广泛应用的兼容性。 当实现与该模式兼容的应用时，在M位模式下的进一步操作可以提供功率节省。
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4.发明授权Multiple address and arithmetic bit-mode data processing device and methods thereof 有权多地址和算术位模式数据处理装置及其方法公开(公告)号：US07805581B2
公开(公告)日：2010-09-28
申请号：US11679590
申请日：2007-02-27
IPC分类号： G06F12/00
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30189 , G06F9/342
摘要： A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.
摘要翻译： 公开了一种数据处理装置及其方法。 数据处理设备可以在三种不同的模式下工作。 在第一N位模式中，数据处理装置根据N位值执行存储器访问，并使用N位值执行算术运算。 在第二种混合N比特/ M比特模式中，数据处理装置基于M比特值执行存储器访问，其中M小于N，并且使用N比特值进行算术运算。 在第三个M位模式中，数据处理设备基于M位值执行存储器访问，并使用M位值执行算术运算。 这三种模式提供与广泛应用的兼容性。 当实现与该模式兼容的应用时，在M位模式下的进一步操作可以提供功率节省。
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公开(公告)号：US20080082843A1
公开(公告)日：2008-04-03
申请号：US11536173
申请日：2006-09-28
IPC分类号： G06F15/00
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.
摘要翻译： 处理器具有取出单元和分支执行单元。 提取单元具有分支预测器。 分支预测器具有分支目标缓冲器和分支方向预测器。 唤醒值是预取在分支获取之后执行的指令提取的数量。 因此，对于第一分支，例如，预测第一尾数。 分支预测器的低功率模式响应于其中命中响应于第一分支的分支目标缓冲器中的命中而启用第一唤醒值的持续时间。
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公开(公告)号：US20090249048A1
公开(公告)日：2009-10-01
申请号：US12057543
申请日：2008-03-28
IPC分类号： G06F9/32
CPC分类号： G06F9/3806 , G06F9/322
摘要： A data processing system includes a branch target buffer (BTB) including a plurality of entries, each entry comprising a tag portion and a long branch indicator. The system also includes segment target address storage circuitry which stores a plurality of segment target addresses, index storage circuitry which stores a plurality of indices for indexing into the segment target address storage circuitry, and control circuitry which receives an instruction address and determines whether the instruction address matches a valid entry in the BTB. When the instruction address matches a valid entry in the BTB and the long branch indicator of the valid entry indicates a long branch, the index storage circuitry provides a selected index of the plurality of indices selected by the received instruction address. In response to the selected index, the segment target address storage circuitry provides a selected segment target address as a higher order target address portion.
摘要翻译： 数据处理系统包括包括多个条目的分支目标缓冲器（BTB），每个条目包括标签部分和长分支指示符。 该系统还包括存储多个分段目标地址的分段目标地址存储电路，索引存储电路，其存储用于索引到分段目标地址存储电路中的多个索引;以及控制电路，其接收指令地址并确定该指令 地址匹配BTB中的有效条目。 当指令地址与BTB中的有效条目匹配，并且有效条目的长分支指示符指示长分支时，索引存储电路提供由接收到的指令地址选择的多个索引的选定索引。 响应于所选择的索引，分段目标地址存储电路将所选择的分段目标地址提供为较高阶目标地址部分。
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7.发明授权Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branch 有权使用唤醒值进行动态分支预测，以使得能够在分支和后续分支之间的预测指令取数的低功率模式公开(公告)号：US07681021B2
公开(公告)日：2010-03-16
申请号：US11536173
申请日：2006-09-28
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.
摘要翻译： 处理器具有取出单元和分支执行单元。 提取单元具有分支预测器。 分支预测器具有分支目标缓冲器和分支方向预测器。 唤醒值是预取在分支获取之后执行的指令提取的数量。 因此，对于第一分支，例如，预测第一尾数。 分支预测器的低功率模式响应于其中命中响应于第一分支的分支目标缓冲器中的命中而启用第一唤醒值的持续时间。
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