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    Method and system for latchup suppression
    1.
    发明授权
    Method and system for latchup suppression 有权
    闭锁抑制方法和系统

    公开(公告)号：US07786756B1

    公开(公告)日：2010-08-31

    申请号：US11241552

    申请日：2005-09-30

    申请人： Vjekoslav Svilan ,  Tien-Min Chen ,  Kleanthes G. Koniaris ,  James B. Burr

    发明人： Vjekoslav Svilan ,  Tien-Min Chen ,  Kleanthes G. Koniaris ,  James B. Burr

    IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K3/00

    CPC分类号： G06F1/3203 ,  G06F1/305 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： Systems and methods of suppressing latchup. In accordance with a first embodiment of the present invention a latchup suppression system comprises a voltage comparator for comparing a voltage applied to a body terminal of a semiconductor device to a reference voltage. The voltage comparator is also for controlling a selective coupling mechanism. The selective coupling mechanism is for selectively coupling the body terminal to a respective power supply. The latchup suppressing system is preferably independent of a voltage supply for applying a voltage to the body terminal.

    摘要翻译： 抑制闭锁的系统和方法。 根据本发明的第一实施例，闭锁抑制系统包括用于将施加到半导体器件的主体端子的电压与参考电压进行比较的电压比较器。 电压比较器也用于控制选择性耦合机构。 选择性耦合机构用于将主体端子选择性地耦合到相应的电源。 闩锁抑制系统优选地独立于用于向身体终端施加电压的电压源。

    BALANCED ADAPTIVE BODY BIAS CONTROL
    2.
    发明申请
    BALANCED ADAPTIVE BODY BIAS CONTROL 审中-公开
    平衡自适应身体偏差控制

    公开(公告)号：US20110221029A1

    公开(公告)日：2011-09-15

    申请号：US13113798

    申请日：2011-05-23

    申请人： Vjekoslav Svilan ,  James B. Burr

    发明人： Vjekoslav Svilan ,  James B. Burr

    IPC分类号： H01L27/02

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator.

    摘要翻译： 平衡自适应体偏置控制的系统和方法。 根据本发明的第一实施例，平衡自适应体偏置控制的方法包括确定用于集成电路的电路的期望的动态条件。 访问对应于期望的动态条件的第一动态指示符。 访问集成电路的第二和第三动态指示器。 通过增量来调整第一体偏置电压，以便在期望的动态条件的方向上改变第一动态指示器。 基于第二动态指示器和第三动态指示器之间的关系来调整第二身体偏置电压。

    Balanced adaptive body bias control
    3.
    发明授权
    Balanced adaptive body bias control 有权
    平衡自适应体偏置控制

    公开(公告)号：US07949864B1

    公开(公告)日：2011-05-24

    申请号：US11238446

    申请日：2005-09-28

    申请人： Vjekoslav Svilan ,  James B. Burr

    发明人： Vjekoslav Svilan ,  James B. Burr

    IPC分类号： G06F1/32 ,  G06F1/24

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator.

    摘要翻译： 平衡自适应体偏置控制的系统和方法。 根据本发明的第一实施例，平衡自适应体偏置控制的方法包括确定用于集成电路的电路的期望的动态条件。 访问对应于期望的动态条件的第一动态指示符。 访问集成电路的第二和第三动态指示器。 通过增量来调整第一体偏置电压，以便在期望的动态条件的方向上改变第一动态指示器。 基于第二动态指示器和第三动态指示器之间的关系来调整第二身体偏置电压。

    MANAGING DYNAMIC CAPACITANCE USING CODE SCHEDULING
    4.
    发明申请
    MANAGING DYNAMIC CAPACITANCE USING CODE SCHEDULING 审中-公开
    使用代码调度管理动态电容

    公开(公告)号：US20150268997A1

    公开(公告)日：2015-09-24

    申请号：US14221750

    申请日：2014-03-21

    申请人： Vjekoslav Svilan ,  David N. Mackintosh

    发明人： Vjekoslav Svilan ,  David N. Mackintosh

    IPC分类号： G06F9/48 ,  G06F1/32

    CPC分类号： G06F9/4893 ,  G06F1/3243 ,  G06F1/329 ,  G06F8/4432 ,  Y02D10/152 ,  Y02D10/24

    摘要： In an embodiment, a processor includes a schedule logic to schedule a set of instructions for execution in an execution logic of the processor and a power analysis logic having a first calculation logic to calculate a maximum dynamic capacitance for at least a portion of the processor and a second calculation logic to calculate a dynamic capacitance estimate for execution of the set of instructions. A rescheduling of the set of instructions may occur based on a comparison of the dynamic capacitance estimate and the maximum dynamic capacitance. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括调度逻辑以调度用于在处理器的执行逻辑中执行的指令集，以及具有第一计算逻辑的功率分析逻辑，以计算处理器的至少一部分的最大动态电容， 用于计算用于执行该组指令的动态电容估计的第二计算逻辑。 可以基于动态电容估计和最大动态电容的比较来重新安排该组指令。 描述和要求保护其他实施例。

    Controlling power gate circuitry based on dynamic capacitance of a circuit
    6.
    发明授权
    Controlling power gate circuitry based on dynamic capacitance of a circuit 有权
    基于电路的动态电容控制电源门电路

    公开(公告)号：US09594412B2

    公开(公告)日：2017-03-14

    申请号：US13996285

    申请日：2012-03-30

    申请人： Vjekoslav Svilan ,  Michael Zelikson ,  Kelvin Kwan ,  Naveen Neelakantam ,  Norbert Unger

    发明人： Vjekoslav Svilan ,  Michael Zelikson ,  Kelvin Kwan ,  Naveen Neelakantam ,  Norbert Unger

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

    摘要： In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有估计逻辑以在多个处理器周期期间估计处理器的处理器电路的动态电容的装置，功率门计算器，用于计算耦合到一个处理器周期的功率门电路的控制值 基于动态电容估计在负载线之间以及电压调节器和处理器电路之间，以及基于控制值来控制电源门电路的阻抗的控制器。 描述和要求保护其他实施例。

    CONTROLLING POWER GATE CIRCUITRY BASED ON DYNAMIC CAPACITANCE OF A CIRCUIT
    7.
    发明申请
    CONTROLLING POWER GATE CIRCUITRY BASED ON DYNAMIC CAPACITANCE OF A CIRCUIT 有权
    基于电路的动态电容控制电源门控电路

    公开(公告)号：US20130275782A1

    公开(公告)日：2013-10-17

    申请号：US13996285

    申请日：2012-03-30

    申请人： Vjekoslav Svilan ,  Michael Zelikson ,  Kelvin Kwan ,  Naveen Neelakantam ,  Norbert Unger

    发明人： Vjekoslav Svilan ,  Michael Zelikson ,  Kelvin Kwan ,  Naveen Neelakantam ,  Norbert Unger

    IPC分类号： G06F1/26

    CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

    摘要： In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有估计逻辑以在多个处理器周期期间估计处理器的处理器电路的动态电容的装置，功率门计算器，用于计算耦合到一个处理器周期的功率门电路的控制值 基于动态电容估计在负载线之间以及电压调节器和处理器电路之间，以及基于控制值来控制电源门电路的阻抗的控制器。 描述和要求保护其他实施例。

    METHODS AND SYSTEMS TO CONTROL POWER GATES DURING AN ACTIVE STATE OF A GATED DOMAIN BASED ON LOAD CONDITIONS OF THE GATED DOMAIN
    9.
    发明申请
    METHODS AND SYSTEMS TO CONTROL POWER GATES DURING AN ACTIVE STATE OF A GATED DOMAIN BASED ON LOAD CONDITIONS OF THE GATED DOMAIN 审中-公开
    基于浇注域的负载条件的浇注域的活动状态期间控制电网的方法和系统

    公开(公告)号：US20150149794A1

    公开(公告)日：2015-05-28

    申请号：US14350548

    申请日：2011-12-27

    申请人： Michael Zelikson ,  Vjekoslav Svilan ,  Norbert Unger ,  Shai Rotem

    发明人： Michael Zelikson ,  Vjekoslav Svilan ,  Norbert Unger ,  Shai Rotem

    IPC分类号： G06F1/26 ,  H03K17/687

    CPC分类号： G06F1/26 ,  G06F1/3243 ,  G06F1/3287 ,  H03K17/687 ,  Y02D10/152 ,  Y02D10/171

    摘要： Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

    摘要翻译： 在电源选通电路的有效状态期间，响应于电路中的负载变化来调节电网和电网门控之间的电阻以维持相对一致的IR下降的方法和系统。 可以基于诸如电压的负载因子的变化来选择性地启用和禁用功率门（PG）的子集，其可以在门控配电网格处和/或接近电力门控电路中的晶体管栅极监视 。 可以执行调整以最小化所监视的电压和参考之间的差异，例如通过逐次逼近或CMS软件。 PG子集可以分布在集成电路（IC）裸片的一个或多个层内，并且可以基于位置被选择性地启用/禁用。 PG可以嵌入集成电路（IC）管芯的下层内，例如在IC管芯的金属层内。