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公开(公告)号：US4097824A
公开(公告)日：1978-06-27
申请号：US772677
申请日：1977-02-28
摘要： A variable equalizer adapted to be fabricated in an integrated circuit structure and having improved compensation characteristics comprises a parallel connection of two circuits, one including a series connection of a first impedance circuit (impedance: Zy) and an input A.C. signal source circuit having a voltage v.sub.i, the other comprising a series connection of a second impedance circuit (impedance: Z.sub.x) and an A.C. signal source circuit having a voltage amplitude v.sub.z which is equal to v.sub.i (K/Z.sub.y).sup.2, where K is a constant, and the second impedance circuit, consists of a variable resistor.
摘要翻译： 适于以集成电路结构制造并具有改进的补偿特性的可变均衡器包括两个电路的并联连接，一个包括第一阻抗电路（阻抗：Zy）的串联连接和具有电压的输入AC信号源电路 vi，另一个包括第二阻抗电路（阻抗：Zx）和具有等于vi（K / Zy）2的电压幅度vz的AC信号源电路的串联连接，其中K是常数，第二 阻抗电路由可变电阻组成。
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公开(公告)号：US4204176A
公开(公告)日：1980-05-20
申请号：US893014
申请日：1978-04-03
CPC分类号： H04B3/145
摘要： A variable equalizer whose frequency characteristic varies in a range of 1-1/Y(f).sup.2when the gain x of a variable amplifier varies from 0 (zero) to .infin. (infinity), and which reduces the number of shaping networks for the variable frequency characteristic.It is constructed of a forward pass circuit which consists of a variable amplifier and a frequency-dependent first circuit connected in the order mentioned between input and output terminals, a feedback pass circuit which is dependent upon the frequency and which feeds-back an output of the variable amplifier to an input thereof, and a feed forward pass circuit which is independent of the frequency and which feeds forward part of the input of the variable amplifier to an output of the first circuit.
摘要翻译： 当可变放大器的增益x从0（零）到INFINITY（无穷大）变化时，其频率特性在1-1 / Y（f）2的范围内变化的可变均衡器，并且这减少了 可变频率特性。 它由正向电路构成，该正向电路由可变放大器和按照输入和输出端之间的顺序连接的频率依赖的第一电路组成，反馈通道电路取决于频率，并且反馈输出 可变放大器到其输入端，以及前馈传输电路，其独立于频率，并且将可变放大器的输入的前部部分馈送到第一电路的输出。
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公开(公告)号：US4122417A
公开(公告)日：1978-10-24
申请号：US796539
申请日：1977-05-13
CPC分类号： H04B3/145
摘要： To form a simple and economical variable equalizer, the equalizer is constructed of a differential amplifier having two input terminals to which an input signal to be equalized and an equalized output signal derived from the output terminal are applied, a first impedance circuit connected between the differential amplifier and the output terminal, and a series circuit having a second impedance circuit and a variable resistor connected in series between the output terminal and a ground terminal.
摘要翻译： 为了形成简单而经济的可变均衡器，均衡器由具有两个输入端的差分放大器构成，输入端被均衡，输入信号得到均衡的输出信号，第一阻抗电路连接在差分 放大器和输出端子，以及具有在输出端子和接地端子之间串联连接的第二阻抗电路和可变电阻器的串联电路。
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公开(公告)号：US4004253A
公开(公告)日：1977-01-18
申请号：US587894
申请日：1975-06-18
摘要： An inductorless variable equalizer comprises input and output terminals. A first transmission network is situated in the forward path between the input and output terminals and has a variable transfer coefficient; second and third transmission networks are situated in the feedback and feedforward paths, respectively, between the input and output terminals. Each of these networks has a fixed transfer coefficient and the transfer coefficients of the feedback and feedforward networks having polarities opposite each other.
摘要翻译： 无电感可变均衡器包括输入和输出端子。 第一传输网络位于输入和输出端之间的前向路径中，具有可变传输系数; 第二和第三传输网络分别位于输入和输出端之间的反馈和前馈路径中。 这些网络中的每一个具有固定的传输系数和具有彼此相反的极性的反馈和前馈网络的传输系数。
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公开(公告)号：US4187479A
公开(公告)日：1980-02-05
申请号：US860098
申请日：1977-12-13
CPC分类号： H04B3/145
摘要： A variable equalizer is provided which, using a single variable resistor, can make compensations in both the directions of the gain side, and the loss side and can set a reference gain as desired.An input signal to be equalized is received as an antiphase input signal of a differential amplifier, an output signal which has been equalized is fed back to the antiphase input signal, and a difference signal between an in-phase input signal and the antiphase input signal is delivered as an output. A resistor is connected between an input terminal and ground, first and second impedance circuits and a variable resistor are connected between an intermediate point of the first-mentioned resistor and ground in the order mentioned, and a voltage at the junction point between the first and second impedance circuits is used as the in-phase input signal.
摘要翻译： 提供了可变均衡器，其使用单个可变电阻器可以在增益侧和损耗侧的两个方向上进行补偿，并且可以根据需要设置参考增益。 接收待均衡的输入信号作为差分放大器的反相输入信号，将均衡的输出信号反馈到反相输入信号，同相输入信号和反相输入信号之间的差分信号 作为输出交付。 电阻器连接在输入端子和地之间，第一和第二阻抗电路和可变电阻器以所述顺序连接在第一个提到的电阻器的中间点和接地之间，并且在第一和第二阻抗电路之间的连接点处的电压 第二阻抗电路用作同相输入信号。
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公开(公告)号：US4080580A
公开(公告)日：1978-03-21
申请号：US738901
申请日：1976-11-04
申请人： Yoshitaka Takasaki , Yasuhiro Kita , Jun'ichi Nakagawa , Kohei Ishizuka , Osamu Yumoto , Yoshinori Nagoya
发明人： Yoshitaka Takasaki , Yasuhiro Kita , Jun'ichi Nakagawa , Kohei Ishizuka , Osamu Yumoto , Yoshinori Nagoya
摘要： In order to realize a precision variable equalizer of little errors by a simple circuit arrangement, a plurality of variable transmission circuits having variable transfer coefficients are connected in series between input and output terminals, and feed-back and feed-forward are applied from input and output sides of the respective variable transmission circuits to input and output portions of the variable equalizer through transmission networks having specified transfer characteristics.
摘要翻译： 为了通过简单的电路布置实现误差小的精度可变均衡器，具有可变传输系数的多个可变传输电路串联连接在输入和输出端子之间，并且从输入和输出端口施加反馈和前馈 各可变传输电路的输出侧通过具有特定传输特性的传输网络来输入和输出可变均衡器的部分。
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公开(公告)号：US4970719A
公开(公告)日：1990-11-13
申请号：US233095
申请日：1988-08-17
申请人： Akihiko Takase , Yoshitaka Takasaki
发明人： Akihiko Takase , Yoshitaka Takasaki
IPC分类号： H04J3/16
CPC分类号： H04J3/1641 , Y10S370/916
摘要： A digital signal multiplexing apparatus comprising variable multiplexers each of which can alter a multiplexed channel format every call in compliance with a subscriber's request, a fixed multiplexer which has a multiplexing capacity integral times as large as the total multiplexing capacity of the variable multiplexers and the multiplexed channel format of which is fixed, and fixed multiplexed signal demultiplexers each of which fixedly demultiplexes signals in a capacity integral times as large as that of each of the variable multiplexers into signals in a capacity equal to the total capacity of the variable multiplexers, wherein the outputs of the fixed multiplexed signal demultiplexers are distributed to the variable multiplexers through a distributing switch network, and the outputs of the variable multiplexers are multiplexed by the fixed multiplexer.
摘要翻译： 一种数字信号复用装置，包括可变多路复用器，每个可以根据用户的请求改变每个呼叫的多路复用信道格式，固定多路复用器具有与可变多路复用器的总复用容量一样大的复用容量， 信道格式固定的固定多路复用信号解复用器，其中固定多路复用信号解复用器固定地将电容量与每个可变多路复用器的整数倍的电容多路分解成等于可变多路复用器的总容量的信号，其中， 固定复用信号解复用器的输出通过分配交换网络分配给可变多路复用器，并且可变多路复用器的输出由固定多路复用器复用。
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公开(公告)号：US4723312A
公开(公告)日：1988-02-02
申请号：US769971
申请日：1985-08-27
CPC分类号： H04B10/502
摘要： A high-speed light emitting diode driver circuit for optical communication systems, in which an impedance circuit is provided between the collector and emitter of a drive transistor, and another impedance circuit is provided on the emitter side. The light emitting diode is connected to the collector side of the drive transistor. The light emitting diode is driven by an input pulse signal applied to the base of the drive transistor.
摘要翻译： 用于光通信系统的高速发光二极管驱动电路，其中阻抗电路设置在驱动晶体管的集电极和发射极之间，另一个阻抗电路设置在发射极侧。 发光二极管连接到驱动晶体管的集电极侧。 发光二极管由施加到驱动晶体管的基极的输入脉冲信号驱动。
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公开(公告)号：US4604745A
公开(公告)日：1986-08-05
申请号：US578791
申请日：1984-02-10
摘要： A method of searching fault locations which is employed in a transmission system comprising a transmitting terminal having a transmitter for transmitting a digital signal; a receiving terminal having a receiver for receiving the digital signal; a plurality of repeaters which are placed between the transmitting and receiving terminals, and each of which receives and amplifies the digital signal from a preceding repeater section and deliver it to a subsequent repeater section; and a plurality of transmission lines for connecting the transmitter with the first repeater, the repeaters with each other and the final repeater with each other and the final repeater with the receiver, respectively. This method comprises the steps of coding an original signal to be transmitted in terms of two kinds of error detecting codes at the transmitting terminal to send out them from the transmitter; detecting an error of a received signal using one of the two kinds of error detecting codes at each repeater thereby to measure the error rate at one repeater section corresponding to each repeater; recoding a decoded received signal using the error detecting code employed to detect the error, and delivering it to a subsequent repeater section, and transmitting signals each of which represents the error rate at each repeater section measured at each repeater, to the transmitting terminal or receiving terminal.
摘要翻译： 一种搜索故障位置的方法，该传输系统包括具有用于发送数字信号的发射机的发射终端; 接收终端，具有接收数字信号的接收机; 放置在发送和接收终端之间的多个中继器，每个中继器从前一个中继器部分接收和放大数字信号，并将其传送到后续中继器部分; 以及多个传输线，用于将发射机与第一中继器连接，中继器彼此相连，最后中继器彼此相连，最后中继器分别与接收机相连。 该方法包括以下步骤：在发送终端根据两种错误检测码对要发送的原始信号进行编码，以从发送器发送出来; 使用每个中继器的两种错误检测码之一检测接收信号的误差，从而测量与每个中继器对应的一个中继器部分的错误率; 使用用于检测误差的检错码重新编码解码的接收信号，并将其传送到后续中继器部分，并且将发送信号分别表示在每个中继器测量的每个转发器部分处的错误率，发送到发送终端或接收 终奌站。
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公开(公告)号：US4320527A
公开(公告)日：1982-03-16
申请号：US66643
申请日：1979-08-15
申请人： Yoshitaka Takasaki
发明人： Yoshitaka Takasaki
摘要： A bit synchronizing system for generating a timing signal corresponding to a transmitted pulse signal is disclosed in which the transmitted pulse signal is converted into a signal in which the number of pulses successively assuming the same polarity is limited to permit detection of frequency, the converted signal is integrated, a peak of integrated values is detected, the output of a voltage-controlled clock generator for generating the timing signal is processed in a similar manner to detect a peak with respect to the output, and the clock generator is controlled by a voltage corresponding to a difference between these two peaks, whereby the frequency of clock signal coincides with the bit rate of the transmitted pulse signal.
摘要翻译： 公开了一种用于产生与发送的脉冲信号相对应的定时信号的位同步系统，其中发送的脉冲信号被转换成其中连续假设相同极性的脉冲数被限制以允许检测频率的信号，转换的信号 被集成，检测到积分值的峰值，以类似的方式处理用于产生定时信号的电压控制时钟发生器的输出，以检测相对于输出的峰值，并且时钟发生器由电压 对应于这两个峰值之间的差值，由此时钟信号的频率与发送的脉冲信号的比特率一致。
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